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Veröffentlichung

Automatic generation of an FPGA based embedded test system for printed circuit board testing

Autoren:
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Heinz- Dietrich Wuttke
Typ:
Konferenz
Status:
akzeptiert
Veröffentlichungsdatum
11.04.2012
Abstract:
This paper describes an FPGA based embedded test system, designed to improve current board level testing methods such as boundary scan. The structure of the test system is based on a layer concept, which facilitates the test system’s automatic generation process by providing the required flexibility and abstraction of the test functions. The main goal is the automatic generation of the test system (hardware and software) based on the board's properties and the specific test algorithm. In this paper, the architecture and the automatic generation flow with emphasis on the software generation process are presented, as well as experimental results obtained when performing an SRAM interconnection test.
Bibtex
Zusatzinfo:
Weiterführender Link
http://www-elec.inaoep.mx/LATW2012/
Weiterführendes Dokument
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6261241&contentType=Conference+Publications&sortType%3Ddesc_p_Publication_Year%26searchField%3DSearch_All%26queryText%3Dwuttke