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Veröffentlichung

ISA configurability of an FPGA test-processor used for board-level interconnection testing

Autoren:
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Heinz- Dietrich Wuttke
Typ:
Konferenz
Status:
akzeptiert
Veröffentlichungsdatum
03.04.2013
Abstract:
This paper presents a study of FPGA test-processor configurability at the instruction set architecture (ISA) level used for board-level interconnection testing. The ISA configurability is used as adaptation mechanism to the test requirements, the FPGA properties, and the devices under test (DUTs). The aim is to show the advantages and limitations of processor configurability at this level, and demonstrate them in the FPGA based test system (FBTS) developed for board-level interconnection testing. The paper presents the test-processor’s concept, adaptation aspects, and architecture, followed by experimental results performed with different processor configurations. Results show the advantages of having a configurable test-processor in terms of performance and FPGA resource utilization.
Bibtex
Zusatzinfo:
@article{10.1109/LATW.2013.6562678,
author = {J.-H. Meza Escobar and J. Sachsse and S. Ostendorff and H.-D. Wuttke},
title = {ISA configurability of an FPGA test-processor used for board-level interconnection testing},
journal ={2013 14th Latin American Test Workshop - LATW},
volume = {0},
isbn = {978-1-4799-0595-9},
year = {2013},
pages = {1-6},
doi = {http://doi.ieeecomputersociety.org/10.1109/LATW.2013.6562678},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
Weiterführender Link
http://tima.imag.fr/conferences/latw2013/
Weiterführendes Dokument
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6562678