Finished

• Dynamic faults (Advanced Seminar)
• Development of an adaptive test environment for testing of a famoly of soft-core processors in VHDL (Bachelor Thesis)
• Developmnent of an intelligent IEEE1149.1 I/O module (Bachelor Thesis)
• Development of a software simulator for the ROBSY processor (Project Work)
• Design of a DUT Model for Flash memory (Bachelor Thesis)
• Development of a SPI flash and I2C EEPROM simulationmodel for FPGA based tests with VHDL and PSL (Project Work)
• Development of a SRAM simulationmodel for FPGA based tests with VHDL (Project Work)
• Entwurf und Ansteuerung eines Boundary Scan Controllers mit optimiertem Datendurchsatz für die Prozessor-Emulation mit unterschiedlichen Protokollen (Bachelor Thesis)
• Development of PSL descriptions for the verification of the ROBSY processor (Project Work)
• FPGA based boundary scan testing for dynamic memory structures (Master thesis)
• GÖPEL ESA Coach Board und Cascon Galaxy Suite (Project Work)
• Hardware profiling for analysis of the ROBSY processor program execution (Project Work)
• HLS und OpenCL FPGA Entwurfstechnologien (Advanced Seminar)
• Implementation of a Mico32 processor on an FPGA (Project Work)
• Implementation of the ROBSY test concept for structural tests using the DE0 development board (Project Work)
• Implementation of a virtual FPGA test instrument for SRAM testing (Project Work)
• Implementation of algorithms for an SD-Card interface in hardware (VHDL) (Project Work)
• Implementation of pipelining for the ROBSY processor (Bachelor Thesis, Master thesis)
• Optimierung der ATE/Prozessor Kommunikationszeiten im Rahmen des ROBSY-Testsystems (Project Work)
• Porting of a predefined soft-core processor to different FPGA platforms (Project Work)
• Research and beginning of the development of an assembler for a soft-core processor on FPGA (Project Work)
• Research and implementation of TPGs for Board-level interconnection test using FPGA based test system (Project Work)
• Research for High Level Decision Diagrams and their function (Advanced Seminar)
• Research of standards IEEE1149.1-2013 IEEEP1687 (Advanced Seminar)
• Research for possibilities of hardware compilation (Advanced Seminar)
• NISC (Advanced Seminar)
• Research about partial dynamic reconfiguration of FPGAs (Advanced Seminar)
• Research about processors with application specific instruction set (ASIP) and configurable processor architectures (Advanced Seminar)
• Research about PSL (Property Specification Language) (Advanced Seminar)
• Research about the OpenJTAG project (Advanced Seminar)
• Research about state of the art of acceleration for boundary scan based testing via JTAG (Advanced Seminar)
• Research of the configuration and instruction-set extension of the NIOS II and Microblaze Processors (Advanced Seminar)
• Research of the SoC Zinq 7000 Family (Advanced Seminar)
• Instruction set extension of the ROBSY processor for pattern generation (Bachelor Thesis)
• System Level Description in VHDL/SystemC/C using the example of a processor (Bachelor Thesis)
• Test of dynamic RAM with Boundary Scan (Advanced Seminar)
• Research of control flow and compare instructions implemented in ARM and MIPS processors (Advanced Seminar)
• Research and classification of FPGA test instruments (Advanced Seminar)
• Investigation and comparison of the synthesis results of different processor variants (Project Work)
• Research of customization methods for soft-core processors (Advanced Seminar)
• Research for Modularization and Parametrization of a VHDL Processor for Automatic Generation of Processor Derivatives (Bachelor Thesis)
• Comparision of the standards IEEE1149.1 and IEEE1149.7 (Advanced Seminar)
• Comparison of different soft-core processor implementations on FPGA (Project Work)