INHALTE
Staff
Project Associate
Dipl.-Math. Jörg Sachße
Dipl.-Math. Jörg Sachße has left our group. The information found here might be out of date.

Thesis or Seminars
Finished
- Analysis and implementation of basic functions for flash tests with FPGAs (Project Work)
- Development of an adaptive test environment for testing of a famoly of soft-core processors in VHDL (Bachelor Thesis)
- Developmnent of an intelligent IEEE1149.1 I/O module (Bachelor Thesis)
- Development of a software simulator for the ROBSY processor (Project Work)
- Development of a SPI flash and I2C EEPROM simulationmodel for FPGA based tests with VHDL and PSL (Project Work)
- Development of a SRAM simulationmodel for FPGA based tests with VHDL (Project Work)
- Development and validation of a microprocessor for FPGA based tests (Diploma Thesis)
- FPGA based boundary scan testing for dynamic memory structures (Master thesis)
- Implementation of a Mico32 processor on an FPGA (Project Work)
- Implementation of algorithms for an SD-Card interface in hardware (VHDL) (Project Work)
- Concept and connection of a test interface for FPGA based processors (Diploma Thesis)
- Modelling and implementation of an network PHY interface (Student research project)
- Porting of a predefined soft-core processor to different FPGA platforms (Project Work)
- Implementation and analysis of dedicated approaches for solving Graph Algorithms (Project Work)
- Research and beginning of the development of an assembler for a soft-core processor on FPGA (Project Work)
- Investigation into evaluation criteria for current boundary scan (BSCAN) based test methods (Advanced Seminar)
- Research for High Level Decision Diagrams and their function (Advanced Seminar)
- Research for possibilities of hardware compilation (Advanced Seminar)
- NISC (Advanced Seminar)
- Research about partial dynamic reconfiguration of FPGAs (Advanced Seminar)
- Research about processors with application specific instruction set (ASIP) and configurable processor architectures (Advanced Seminar)
- Research about PSL (Property Specification Language) (Advanced Seminar)
- Research about the OpenJTAG project (Advanced Seminar)
- Research about state of the art of acceleration for boundary scan based testing via JTAG (Advanced Seminar)
- Research for generation of VHDL from UML models (Advanced Seminar)
- System Level Description in VHDL/SystemC/C using the example of a processor (Bachelor Thesis)
- Implementation of an UML parser and VHDL generator (Project Work)
- Research and implementation of an automatic VHDL generation of elementary functions for test algorithms in FPGAs (Bachelor Thesis)
- Investigation and comparison of the synthesis results of different processor variants (Project Work)
- Research for Modularization and Parametrization of a VHDL Processor for Automatic Generation of Processor Derivatives (Bachelor Thesis)
- Comparision of the standards IEEE1149.1 and IEEE1149.7 (Advanced Seminar)
- Comparison of different soft-core processor implementations on FPGA (Project Work)