"BIST Analyzer: a Training Platform for SoC Testing", Frontiers in Education Conference (FIE07), Milwaukee, USA, October 10-13.
Dr.-Ing. Heinz- Dietrich Wuttke
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- The increasing complexity of recent VLSI circuits and transition to multi-core System-on-Chip (SoC) and Network-on-Chip (NoC) paradigms has made testing (including planning, test generation and scheduling) one of the
most complicated and time-consuming problems in the domain of digital design. The semiconductor manufacturing industry is inevitably moving towards test compression and self-testing approaches that allow either to efficiently feed test data to individual system cores or to initially design self-testable cores. The key concepts applied in modern testing are based on data coding, data compression, cryptography, field theory, signature analysis, Boolean algebra, automata theory, linear programming, evolutionary optimization, solid-state physics and many-many other advanced areas of modern science and technology.
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