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Publication

Automated design error localization in RTL designs

Authors:
Dr.-Ing. Maksim Jenihhin
Anton Tsepurov
Valentin Tihhomirov
Dr. Jaan Raik
Hanno Hantson
Raimund Ubar
Günter Bartsch
Dr.-Ing. Jorge Hernán Meza Escobar
Dr.-Ing. Heinz- Dietrich Wuttke
Typ:
Journal
Status:
accepted
Date of publication
06/28/2013
Abstract:
Rapidly growing systems complexity has led to increasing design costs and verification has become one of the most expensive tasks in the design process. While several approaches and tools focusing on identifying the occurrences of errors exist, scalable solutions for design error, or bug,localization are missing. On one hand, the designer is faced with too much information provided by the verification tools. On the other hand, there is not enough information in order to unambiguously locate the bug. Therefore, manual bug localization activity is very time consuming and there is a need for automated approaches.
In this paper we consider the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification and, thus, design error
localization is required.
Bibtex
Additional Info:
Digital Object Identifier: 10.1109/MDAT.2013.2271420
External link
http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6549113&sortType%3Ddesc_p_Publication_Year%26queryText%3Dwuttke
Documents
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6549113