Modeling Timing Constraints for Automatic Generation of Embedded Test Instruments
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dr.-Ing. Heinz- Dietrich Wuttke
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- This paper describes how to model timing constraints for basic control functions of embedded test instruments in the area of structural circuit board testing. It describes how the timing information is extracted from data sheets, modeled in a domain specific language and processed to obtain the shortest possible test time for the automatically generated embedded test instrument. The generated hardware description of the test instrument is supplied as a co-processor to an embedded testprocessor.
This enables the processor to access the devices-undertest with correct and optimal timing, to speed up the test process and to allow at-speed testing.
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