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Automated Design Error Localization in RTL Designs

Authors:
Dr.-Ing. Maksim Jenihhin
Anton Tsepurov
Valentin Tihhomirov
Dr. Jaan Raik
Hanno Hantson
Raimund Ubar
Günter Bartsch
Dr.-Ing. Jorge Hernán Meza Escobar
Dr.-Ing. Heinz- Dietrich Wuttke
Typ:
Journal
Status:
accepted
Date of publication
01/11/2014
Abstract:
This paper considers the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification and, thus, design error localization is required. However, due to the enormous complexity of modern Register-Transfer Level (RTL) designs, several bugs may escape verification and are consequently handled by post-silicon validation.
Bibtex
External link
http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6221038
Documents
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6549113