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Architecture of an adaptive Test System built on FPGA

Authors:
Dipl.-Math. Jörg Sachße
Dr.-Ing. Heinz- Dietrich Wuttke
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Typ:
Conferences
Status:
accepted
Date of publication
02/24/2011
Abstract:
This paper describes an FPGA based test system, designed to improve current board level testing methods such as boundary scan. The design of the system architecture is based on a layer concept that provides important advantages for its flexibility. This makes it possible to reconfigure and automatically generate the test system determined by the board's properties and the specific test algorithms. The principal system components are a soft-core processor, a debug and communication interface, and co-processing units built from component models. The system architecture and its relation to the layer concept are presented, mentioning basic properties such as FPGA vendor independency and JTAG compatibility.
Bibtex
Additional Info:
extended BibTex:
@incollection {springerlink:10.1007/978-3-642-19137-4_8,
author = {Sachße, Jörg and Wuttke, Heinz-Dietrich and Ostendorff, Steffen and Meza Escobar, Jorge},
affiliation = {Integrated Communication Systems Group, Ilmenau University of Technology, P.O.B. 100565, 98684 Ilmenau, Germany},
title = {Architecture of an Adaptive Test System Built on FPGAs},
booktitle = {Architecture of Computing Systems - ARCS 2011},
series = {Lecture Notes in Computer Science},
editor = {Berekovic, Mladen and Fornaciari, William and Brinkschulte, Uwe and Silvano, Cristina},
publisher = {Springer Berlin / Heidelberg},
isbn = {},
pages = {86-97},
volume = {6566},
url = {http://dx.doi.org/10.1007/978-3-642-19137-4_8},
note = {10.1007/978-3-642-19137-4_8},
year = {2011}
}
External link
http://conferences.dei.polimi.it/arcs2011/
Documents
http://www.springerlink.com/content/61056x71j1k43vhg/fulltext.pdf