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Student projects

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Integrated HW/SW Systems

Topic

Integration of internet based services into embedded devices

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Prof. h. c. Karsten Henke
Dr.-Ing. Steffen Ostendorff
Students:
Christian Lutze
Status:
finished
Abstract:
not available

Topic

Development of demo applications for the NEEK system

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Students:
Marian Sauer
Status:
finished
Abstract:
not available

Topic

Comparision of the standards IEEE1149.1 and IEEE1149.7

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Steffen Krug
Status:
finished
Abstract:
not available

Topic

Possibilites and limitations of ZamiaCAD

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Students:
Paul Harig
Status:
finished
Abstract:
not available

Topic

Research for possibilities of automatic VHDL generation

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Students:
Torsten Reissland
Status:
finished
Abstract:
not available

Topic

Porting of a predefined soft-core processor to different FPGA platforms

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Alexander Krahn
Erik Wolf
Status:
finished
Abstract:
not available

Topic

Research and beginning of the development of an assembler for a soft-core processor on FPGA

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Daniel Stanko
Status:
finished
Abstract:
not available

Topic

Comparison of different soft-core processor implementations on FPGA

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Alexander Krahn
Erik Wolf
Status:
finished
Abstract:
not available

Topic

Research about processors with application specific instruction set (ASIP) and configurable processor architectures

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Stefan Bambl
Status:
finished
Abstract:
not available

Topic

Development of an adaptive test environment for testing of a famoly of soft-core processors in VHDL

Kind of work:
Bachelor Thesis
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Christian Hergenröder
Status:
finished
Abstract:
This thesis deals with the design of an adaptive testbench for verifying the instruction set of a family of soft-core processors.
The various processors are given as a hardware description in VHDL, which is why the testbench will also be developed in VHDL. At rst some basics about veri cation,
particularly with regard to selfchecking testbenches, are presented. After gathering the requirements, a design that meets these ones is developed. In the implementation
chapter, the results of the practical work are presented, in which the individual components will be explained in detail. Thereafter, the correct functionality of the testbench is verified. At last a short perspective for possible further development is given.

Topic

Research about state of the art of acceleration for boundary scan based testing via JTAG

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
René Scheibe
Status:
finished
Abstract:
not available

Topic

Analysis of the IJTAG standard

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Heinz- Dietrich Wuttke
Dr.-Ing. Steffen Ostendorff
Students:
Marc Kaiser
Status:
finished
Abstract:

Topic

Research of possibilities and implementation of a variable connection between a processor and I/O components

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Students:
René Scheibe
Status:
finished
Abstract:

Topic

Modelling and implementation of an network PHY interface

Kind of work:
Student research project
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dipl.-Math. Jörg Sachße
Students:
René Schmidt
Status:
finished
Abstract:

Topic

Implementation of an UML parser and VHDL generator

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Heinz- Dietrich Wuttke
Dr.-Ing. Steffen Ostendorff
Dipl.-Math. Jörg Sachße
Students:
Patrick Hanisch
Tim Schuschies
Status:
finished
Abstract:

Topic

Research for generation of VHDL from UML models

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Heinz- Dietrich Wuttke
Dr.-Ing. Steffen Ostendorff
Dipl.-Math. Jörg Sachße
Students:
Philipp Wagner
Status:
finished
Abstract:

Topic

FPGA based boundary scan testing for dynamic memory structures

Kind of work:
Master thesis
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Christian Hergenröder
Status:
finished
Abstract:
not available

Topic

Concept and connection of a test interface for FPGA based processors

Kind of work:
Diploma Thesis
Supervisor:
Dr.-Ing. Heinz- Dietrich Wuttke
Dr.-Ing. Steffen Ostendorff
Dipl.-Math. Jörg Sachße
Students:
Christian Boigs
Status:
finished
Abstract:
This diploma thesis is part of a project to develop a holistic approach of an architecture for tests
of FPGA based systems with Boundary Scan.
The aim of this work is to inform with relevant literature about standards and approaches of
interfaces for testing and debugging and to concept such an interface in dependence on this
information and also own perception. Originating in this concept an exemplary implementation
should be realized.
At first the fundamentals of test concepts up to processor based test, which the project belongs to, are presented. Afterwards several standards concerning testing and debugging are looked at, in case they are relevant for the project or represent alternatives. In the conception some important design ideas are captured and explained and in the following section the implementation of an exemplary interface including design, function and test is described. Based on the implementation also some possible modifications and expansions of the interface are outlined. For the purpose of the documentation all implemented instructions are attached in the appendix as a list with a
short description and an example.

Topic

Concept and implementation of a central control unit for mobile aircrafts based on FPGA

Kind of work:
Diploma Thesis
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Thomas Volkert
Students:
Thomas Hertwig
Status:
finished
Abstract:

Topic

Analysis and implementation of basic functions for flash tests with FPGAs

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dipl.-Math. Jörg Sachße
Students:
Reza Balaghiasefi
Orlando Petsch
Status:
finished
Abstract:

Topic

Efficient FAT32 implementation for a FPGA/µC System

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Students:
Stephan Simon
Stefan Vogel
Status:
finished
Abstract:

Topic

Möglichkeiten der integrierten USB2.0-Funktionalität moderner Mikrocontroller

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Prof. h. c. Karsten Henke
Students:
Johannes Both
Folker Schwesinger
Status:
finished
Abstract:

Topic

Analyse und prototypische Implementierung JTAG-baiserter PLD-Programmierung

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Students:
Alexander Krahn
Erik Wolf
Status:
finished
Abstract:

Topic

Research and implementation of approaches for short distance 3D-location of mobile platforms

Kind of work:
Student research project
Supervisor:
Dipl.-Ing. Alexander Krause
Students:
Thomas Schmidt
Status:
finished
Abstract:

Topic

Development of a SRAM simulationmodel for FPGA based tests with VHDL

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
René Scheibe
Status:
finished
Abstract:
not available

Topic

access of an eDIP display for observation and control functions

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Students:
Christian Lehmann
Status:
finished
Abstract:

Topic

Emulation-Based Debugging

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Heinz- Dietrich Wuttke
Dr.-Ing. Steffen Ostendorff
Students:
René Schmidt
Status:
finished
Abstract:

Topic

Concept for functional tests of a vehicle control system

Kind of work:
Diploma Thesis
Supervisor:
Dr.-Ing. Heinz- Dietrich Wuttke
Students:
Stefan Schweinitzer
Status:
finished
Abstract:

Topic

Recherche und Analyse von Einsatzmöglichkeiten für FPGAs in Mikrokoptersteuerungen

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Prof. h. c. Karsten Henke
Dr.-Ing. Steffen Ostendorff
Students:
Thomas Hertwig
Status:
finished
Abstract:

Topic

Programming of a FPGA based videosnake

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Heinz- Dietrich Wuttke
Dr.-Ing. Steffen Ostendorff
Students:
René Hutschenreuter
René Schmidt
Status:
finished
Abstract: