A Generic Debug Interface for IP-Integrated Assertions
- Kind of work:
- Diploma Thesis
Dr.-Ing. Heinz- Dietrich Wuttke
- Nowadays design projects require fast time to market and solid verification throughout the entire design flow. Many concept have been tried to raise the level of abstraction during the design phase, where model-based design is the most promising one. In this thesis a model-based approach will be extended to allow automatic generation of an assertion interface for IPs corresponding to the Inneon Essence metamodel. Furthermore an own datamodel will be modeled to capture the specific needs for a general silicon-on-debug assertion Interface and the realworld work with it.
This thesis was developed as a part of WP 1 of the ESCI Open SoC Design Platform for Reuse and Integration of IPs (SPRINT) project.