Concept and connection of a test interface for FPGA based processors
- Kind of work:
- Diploma Thesis
Dr.-Ing. Heinz- Dietrich Wuttke
Dr.-Ing. Steffen Ostendorff
Dipl.-Math. Jörg Sachße
- This diploma thesis is part of a project to develop a holistic approach of an architecture for tests
of FPGA based systems with Boundary Scan.
The aim of this work is to inform with relevant literature about standards and approaches of
interfaces for testing and debugging and to concept such an interface in dependence on this
information and also own perception. Originating in this concept an exemplary implementation
should be realized.
At first the fundamentals of test concepts up to processor based test, which the project belongs to, are presented. Afterwards several standards concerning testing and debugging are looked at, in case they are relevant for the project or represent alternatives. In the conception some important design ideas are captured and explained and in the following section the implementation of an exemplary interface including design, function and test is described. Based on the implementation also some possible modifications and expansions of the interface are outlined. For the purpose of the documentation all implemented instructions are attached in the appendix as a list with a
short description and an example.