Development of an adaptive test environment for testing of a famoly of soft-core processors in VHDL
- Kind of work:
- Bachelor Thesis
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
- This thesis deals with the design of an adaptive testbench for verifying the instruction set of a family of soft-core processors.
The various processors are given as a hardware description in VHDL, which is why the testbench will also be developed in VHDL. At rst some basics about verication,
particularly with regard to selfchecking testbenches, are presented. After gathering the requirements, a design that meets these ones is developed. In the implementation
chapter, the results of the practical work are presented, in which the individual components will be explained in detail. Thereafter, the correct functionality of the testbench is verified. At last a short perspective for possible further development is given.