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Integrated HW/SW Systems

Topic

Extension of the GAL programmer

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Prof. h. c. Karsten Henke
Dr.-Ing. Steffen Ostendorff
Status:
finished
Abstract:

Topic

Analysis and conceptual design of FPGA-based structural tests of sensor circuit boards

Kind of work:
Master thesis
Supervisor:
Dr.-Ing. Heinz- Dietrich Wuttke
Dr.-Ing. Steffen Ostendorff
Students:
Stefan Vogel
Status:
finished
Abstract:

Topic

Development of a software simulator for the ROBSY processor

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Alexander Katzmann
Christian Lutze
B. sc. Tobias Vietzke
Status:
finished
Abstract:

Topic

Smart Grid Maturity Model (Group Studies)

Supervisor:
Dipl.-Ing. Sven Bohn
Students:
Banuchandar Mohanarama
Chaitali Bafna
Abilasha Chandrasekaran
Status:
finished
Abstract:

Topic

Development of PSL descriptions for the verification of the ROBSY processor

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Jorge Hernán Meza Escobar
Students:
Daniel Stanko
Status:
finished
Abstract:
not available

Topic

Implementation of pipelining for the ROBSY processor

Kind of work:
Bachelor Thesis, Master thesis
Supervisor:
Dr.-Ing. Jorge Hernán Meza Escobar
Students:
Paul Harig
Status:
finished
Abstract:

Topic

Investigation and comparison of the synthesis results of different processor variants

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Paul Harig
Karsten Hohmeier
Torsten Reissland
Status:
finished
Abstract:

Topic

Research of the configuration and instruction-set extension of the NIOS II and Microblaze Processors

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Jorge Hernán Meza Escobar
Students:
Daniel Seichter
Status:
finished
Abstract:

Topic

Research about altera programming schemes and implement it on an embedded system

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Prof. h. c. Karsten Henke
Dr.-Ing. Steffen Ostendorff
Students:
Silvia Krug
Status:
finished
Abstract:
Not available

Topic

Developmnent of an intelligent IEEE1149.1 I/O module

Kind of work:
Bachelor Thesis
Supervisor:
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Daniel Stanko
Status:
finished
Abstract:

Topic

Research and implementation of an automatic VHDL generation of elementary functions for test algorithms in FPGAs

Kind of work:
Bachelor Thesis
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dipl.-Math. Jörg Sachße
Students:
Orlando Petsch
Status:
finished
Abstract:
not available

Topic

Implementation and analysis of dedicated approaches for solving Graph Algorithms

Kind of work:
Project Work
Supervisor:
Dipl.-Math. Jörg Sachße
Students:
Tom Buschbeck
Status:
finished
Abstract:
Not available

Topic

NISC

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
René Scheibe
Status:
finished
Abstract:
k.A.

Topic

Development of a SPI flash and I2C EEPROM simulationmodel for FPGA based tests with VHDL and PSL

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Christian Hergenröder
Status:
finished
Abstract:
Not available

Topic

Implementation and demonstration of partial dynamic reconfiguration of FPGAs

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Students:
Wilhelm Winterstein
Status:
finished
Abstract:

Topic

Research about partial dynamic reconfiguration of FPGAs

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Christian Hergenröder
Status:
finished
Abstract:
not available

Topic

Research about the usability of Java RMI as communication interface to FPGA based co-processors

Kind of work:
Bachelor Thesis
Supervisor:
Dr.-Ing. Steffen Ostendorff
Students:
Folker Schwesinger
Status:
finished
Abstract:
This thesis describes the connection of FPGA–based co–processors to standard PC systems.
The two user applications running on the subsystems both use Java technology. The concept
for data transmissions between the Java applications is implemented in a demonstration system.
The presented system consists of a standard PC and the Xilinx ML505 Evaluation Platform.
On the FPGA board the Java Optimized Processor (JOP) is used as a Java–based co–processor.
A transport system similar to Java Remote Method Invocation (RMI) is developed to allow the
exchange of Java objects via PCI Express. In this context the thesis shows that Java RMI can not
be used directly for the communication between both Java applications resident on the FPGA
system and the standard PC. The proposed demonstration system is used in a radar processing
application developed by EADS Deutschland GmbH. The purpose of the radar application is
to evaluate a framework of tools developed during the Java Environment for Parallel Realtime
Development (JEOPARD) project which is partially funded by the European Comission.

Topic

Research about the OpenJTAG project

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Wilhelm Winterstein
Status:
finished
Abstract:

Topic

Implementation of a Mico32 processor on an FPGA

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Tim Venter
Status:
finished
Abstract:
Not available

Topic

Design of an automatic documentation of state machines from VHDL code

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Students:
Folker Schwesinger
Status:
finished
Abstract:
Not available

Topic

Research for Modularization and Parametrization of a VHDL Processor for Automatic Generation of Processor Derivatives

Kind of work:
Bachelor Thesis
Supervisor:
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Stefan Vogel
Status:
finished
Abstract:

Topic

Kompressionsalgorithmen

Kind of work:
Advanced Seminar
Supervisor:
Dipl.-Inf. Philipp Drieß
Dipl.-Inf. Stephan Bärwolf
Students:
Michael Kirchhoff
Status:
finished
Abstract:

Topic

Research about PSL (Property Specification Language)

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
A. Philipp Höhne
Status:
finished
Abstract:

Topic

Research for High Level Decision Diagrams and their function

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Pavlo Kalashnikov
Status:
finished
Abstract:

Topic

Control Group Scheduler

Kind of work:
Advanced Seminar
Supervisor:
Dipl.-Inf. Philipp Drieß
Dipl.-Inf. Stephan Bärwolf
Students:
Gabriel Welsche
Status:
finished
Abstract:

Topic

Survey about SDR platforms for MAC layer development

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Andre Puschmann
Status:
finished
Abstract:

Topic

System Level Description in VHDL/SystemC/C using the example of a processor

Kind of work:
Bachelor Thesis
Supervisor:
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Tafil Kajtazi
Status:
finished
Abstract:

Topic

Implementation of algorithms for an SD-Card interface in hardware (VHDL)

Kind of work:
Project Work
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
B. sc. Tobias Vietzke
Status:
finished
Abstract:
not available

Topic

Research about possibilities of resource estimation for RTDL designs for FPGAs

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Students:
Daniel Stanko
Status:
finished
Abstract:
not available

Topic

Research for possibilities of hardware compilation

Kind of work:
Advanced Seminar
Supervisor:
Dr.-Ing. Steffen Ostendorff
Dr.-Ing. Jorge Hernán Meza Escobar
Dipl.-Math. Jörg Sachße
Students:
Christian Hergenröder
Status:
finished
Abstract:
not available