Proposing hydrosilane-free cost-effective micro and nano SiO2 films by atmospheric pressure chemical vapor deposition for photovoltaic applications

by Esmail Issa1, 2,  Henning Nagel1 and Edda Rädlein2

1Fraunhofer Institute for Solar Energy Systems (ISE), Heidenhofstraße 2, 79110 Freiburg, Germany
2TU Ilmenau, Fakultät für Maschinenbau, Institut für Werkstofftechnik, FG Anorganische-nichtmetallische Werkstoffe, Gustav-Kirchhoff-Straße 6, D-98693 Ilmenau, Germany

In today’s thin solid films’ world there are several well-known techniques for the deposition of SiO2 films, e.g. low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), spray pyrolysis (SP), sol-gel deposition (SGD) and atmospheric pressure chemical vapor deposition (APCVD). Thus far, PECVD has been the most widespread technique, yet at low substrate temperature, the SiO2 films prepared this way tend to be porous [1]. Such EPCVD SiO2 films can be employed as optical coatings on glass because of their low refractive index. However, often dense SiO2 films and thus high deposition temperatures are desired, e.g. if protective coatings are needed. Apart from the high deposition temperature another cost driver for the equipment price are the vacuum tools. SP, SGD and APCVD operate at atmospheric pressure and therefore are favorable when it comes to costs. Among those, APCVD holds the advantage of using gases as reactant precursors in contrast to liquids. Consequently, crack-free dense films with good step coverage can readily be obtained. Conventional APCVD of SiO2 utilizes the reactants hydrosilane (SiH4) and dinitrogen monoxide (N2O) at deposition temperatures between 250 °C and 400 °C [2]. Because SiH4 abruptly catches fire when it comes in contact with air, special safety measures are required. In our newly developed setup a SiH4 free SiO2 CVD technique operated under atmospheric conditions is utilized. This drastically reduces the equipment price and complexity. By subsequent annealing of the as-deposited films at temperatures between 200 and 400 °C for 1 – 10 min their relevant etch, rates in alkaline and acidic liquids are minimized so that they are well suited for protective layers in different applications. By way of examples this work demonstrates single-side texturing and reduction of parasitic metal deposition during electroplating of crystalline Si solar cells’ front side metallization.

This room-temperature process allows for manufacturing the APCVD equipment completely out of thermoplastic materials. This leads to the additional advantage of the decrease in possible metal contamination in substrates and coatings. The equipment is made by fused deposition modelling, also known as 3D printing technology, so that it can be tailored to the needs of e.g. different wafer sizes or substrate shapes. The thermoplastic material utilized in the 3D printing process is polylactid acid. Our present setup is a single wafer reactor suitable for 6-inch Si wafers (the setup is not shown here). The reactive gases are mixed in an APCVD reactor and form the SiO2 films on the substrate. This deposition is driven by surface reaction mechanisms contrast to the conventional APCVDs known to be controlled by gas-phase reaction. Parasitic deposition on the reactor walls is minimized by a special coating (explained elsewhere). The ratio of the front and rear side SiO2 layer thickness on a wafer can easily be adjusted by variation of the distance between the wafer and the deposition chuck of the APCVD reactor. In the applications investigated in this work, the wafers were positioned close to the deposition chuck in order to ensure single side SiO2 coating. An inline deposition system would be conceivable with a gas-tight transport belt. In our first application which is single-side texturing we coated polished 4 inch FZ Si wafers on one side with about 180 nm SiO2 in 12 min at room temperature. Subsequently, the wafers were annealed at 300 °C for 1 min on a hotplate (to densify the deposited films) and immersed in an alkaline texturing solution for 6 min at 80 °C. Our second application is parasitic plating elimination on CZ Si passivated emitter and rear contacted (PERC) solar cells. Alkaline textured p-type cells featuring screen-printed full area Al rear side metallization and SiNx antireflection coating (ARC) on the front side were employed. About 90 nm thick SiO2 was partly or full area deposited on top of the SiNx ARC and annealed at 400 °C for 10 min. A 5 busbars and 110 fingers contact grid layout was laser ablated, single side HF dipped for 20 s and electroplated with a Ni/Cu/Ag metal stack. The uniformity of the deposited SiO2 films was inspected on shiny etched reference wafers using ellipsometry and the wafers’ cross sections were investigated by scanning electron microscopy (SEM). The performance of the alkaline texture was characterized by hemispherical reflectance measurements.

SEM investigations revealed that dense SiO2 films without pores or cracks were deposited on wafers even if the SiO2 is very thick (about 760 nm), shown in Fig. 1. For our standard process, we obtained a deposition rate of 15 nm/min and a SiO2 thickness variation of ± 10 on the upper side of the 6-inch Si wafers, shown in Fig. 2. In case of simultaneous double side deposition, we measured a SiO2 thickness variation of ± 6 % on the lower wafer side, shown in Fig. 3. In our first application the alkaline texturing solution uniformly etched about 100 nm of the annealed SiO2 protective layer at 80 °C in 6 min. Seen in Fig. 4 (right), no pinholes were formed so that the SiO2 coated wafer side was as smooth as before texturing. In contrast, the unprotected wafer side was textured with random pyramids as intended, seen in Fig. 4 (left). Fig. 5 depicts measured reflectance of the front and rear side of the FZ Si wafer shown in Fig. 4. The measurements sufficiently comply with anticipated values as can be seen from the match with a measurement on an alkaline textured reference wafer (without SiO2 coating) and with a simulated curve, respectively. The simulation was performed by means of the transfer matrix method assuming a 84 nm thick SiO2 layer on c-Si. In our second application an about 90 nm thick annealed SiO2 layer efficiently acted as a protective layer against parasitic plating. The SiO2 coated areas of the cells were practically free of unwanted metal deposition whereas there was massive parasitic plating in the uncoated areas as shown in Fig 6.

The newly developed APCVD setup provides a simple and tailorable approach for the deposition of SiO2 films on virtually every substrate material at room temperature. Depending on the features of the films needed, e.g. etch resistance; it is advantageous to anneal them at elevated temperature after deposition. Because of the used non-flammable and inexpensive gases, the costs of the deposition equipment and of the operations are low. The presented simple APCVD SiO2 process can find several applications in photovoltaics, two of those are demonstrated in this work. Another application is e. g. the deposition of an insulating SiO2 layer on the transparent conducting oxide of heterojunction solar cells for preparation of locally plated Ni/Cu/Ag front side metallization. See the original publications [3-5] for further details.


[1] H. Nagel, A. Metz and R. Hezel, Porous SiO2 Films Prepared by Remote Plasma-Enhanced Chemical Vapour Deposition - a Novel Antireflection Coating Technology for Photovoltaic Modules, Solar Energy Materials & Solar Cells 65 (2001) 71 – 77
[2] S. Sivoththaman, P. De Schepper, W. Laureys, Johan F. Nijs and Robert P. Mertens, Improving Low-Temperature APCVD SiO2 Passivation by Rapid Thermal Annealing for Si Devices, IEEE Electron Device Letters 19 (1998), 505 – 507
[3] E. Issa, H. Nagel, J. Bartsch, M. Glatthaar, E. Rädlein, Application of hydrosilane-free atmospheric pressure chemical vapor deposition of SiOx films in the manufacture of crystalline silicon solar cells, Thin Solid Films. 713 (2020).
[4] E. Issa, H. Nagel, L. Guzik, H. Javanbakht, E. Coron, E. Rädlein, M. Glatthaar and S. W. Glunz, Plated Front Side Metallization on Transparent Conducting Oxide, 36th Eur. Photovolt. Sol. Energy Conf. Exhib. Marseille, France (2019) 431– 435.
[5] H. Nagel, E. Issa, T. Nagel, M. Glatthaar and S. W. Glunz, Hydrosilane-Free Low-Cost APCVD of SiO2 Films for Crystalline Si Solar Cell Applications, in: 36th Eur. PV Sol. Energy Conf. Exhib., Marseille, France, (2019) 419 – 422


Author for correspondence: Esmail Issa
+49 (0)3677 69-3247



Fig. 1: Scanning electron microscope images taken of cross sections of 575 nm and 764 nm thick APCVD SiO2 films deposited on polished FZ Si wafers, respectively. Dense films deposited intimately upon the Si planar surface are depicted.
Fig. 2: Photos of a shiny-etched 6 inch CZ Si wafer after APCVD of SiO2 for 6 min at room temperature showing the film thickness in nm measured by ellipsometry. Left: Upper wafer side. Right: Lower wafer side that lays on the deposition chuck of the APCVD reactor. The horizontal lines visible in the photo are reflections of saw marks on the wafer and are not correlated to the APCVD process.
Fig. 3: Photos of a shiny-etched 6 inch CZ Si wafer after APCVD of SiO2 for 6 min at room temperature showing the film thickness in nm measured by ellipsometry. Left: Upper wafer side. Right: Lower wafer side that was locat-ed at a distance of 60 mm above the deposition chuck of the APCVD reactor during operation.
Fig. 4: Scanning electron microscope pictures taken of cross sections of a polished FZ Si wafer after alkaline texture at 80 °C for 6 min. Left: Uncoated front side of the wafer. Right: APCVD SiO2 coated rear side.
Fig. 5: Measured hemispherical reflectance of the front and rear side of the FZ Si wafer shown in Fig. 4.
Fig. 6: Photo of an alkaline textured CZ Si solar cell after plating of the front side metallization. The part of the cell that was not coated with a SiO2 capping layer on top of the SiNx antireflection coating reveals massive parasitic plating in between the finger lines. The APCVD SiO2 coated part of the cell shows practically no parasitic plating.