Publications

Convolutional Neural Networks (CNN) are widely used for image classification and have achieved significantly accurate performance in the last decade. However, they require computationally intensive operations for embedded applications. In recent years, FPGA-based CNN accelerators have been proposed to improve energy efficiency and throughput. While dynamic partial reconfiguration (DPR) is increasingly used in CNN accelerators, the performance of dynamically reconfigurable accelerators is usually lower than the performance of pure static FPGA designs. This work presents a dynamically reconfigurable CNN accelerator architecture that does not sacrifice throughput performance or classification accuracy. The proposed accelerator is composed of reconfigurable macroblocks and dynamically utilizes the device resources according to model parameters. Moreover, we devise a novel approach, to the best of our knowledge, to hide the computations of the pooling layers inside the convolutional layers, thereby further improving throughput. Using the proposed architecture and DPR, different CNN architectures can be realized on the same FPGA with optimized throughput and accuracy. The proposed architecture is evaluated by implementing two different LeNet CNN models trained by different datasets and classifying different classes. Experimental results show that the implemented design achieves higher throughput than current LeNet FPGA accelerators.

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.

Convolutional Neural Networks (CNNs) are a very popular class of artificial neural networks. Current CNN models provide remarkable performance and accuracy in image processing applications. However, their computational complexity and memory requirements are discouraging for embedded realtime applications. This paper proposes a highly optimized CNN accelerator for FPGA platforms. The accelerator is designed as a LeNet CNN architecture focusing on minimizing resource usage and power consumption. Moreover, the proposed accelerator shows more than 2x higher throughput in comparison with other FPGA LeNet accelerators with reaching up 14 K images/sec. The proposed accelerator is implemented on the Nexys DDR 4 board and the power consumption is less than 700 mW which is 3x lower than the current LeNet architectures. Therefore, the proposed solution offers higher energy efficiency without sacrificing the throughput of the CNN.

FPGAs (Field programmable Gate Arrays) are useful compo-nents for embedded systems. In combination with Systems-on-Chip and Networks-on-Chip they enable flexible system solutions. Reliability and fault tolerance in such systems often is implemented by adding components for redundancy. Due to constraints in structural resources of FPGA chips, this approach in many cases does not provide adequate solutions. Indirect re-dundancy combined with universal component monitoring is a solution for failsafe Systems-on-Chip / Networks-on-Chip appli-cations in such situations.

In dieser Dissertation werden Modelle und Techniken zur Prozessplanung und Ablaufsteuerung unter Unsicherheit behandelt. Forschungs- und Entwicklungsprojekte sind kompliziert zu überwachen und zu steuern, weil die Bearbeitungszeiten von Aufgaben variieren können und das genaue Prozessmodell am Anfang nicht vollständig bekannt ist. Die Nutzung verschiedener Ressourcen, einschließlich Personal und Ausrüstung (Computer, Geräte usw.), beeinflusst auch den Zeitplan und die Kosten der Projekte. Bayes'sche Netze werden verwendet, um den Einfluss von Unsicherheiten darzustellen und zu messen. Dadurch ist es möglich, Informationen über die Projektstruktur in den Entscheidungsprozess einzubeziehen. Das Modell baut auf einem Prozessmodell eines Projekts auf. Schätzungen der Aufgabendauer werden als Zufallsvariablen für die Inferenz verwendet. Fuzzy-Logik, eine häufige Methode zur linguistischen Beschreibung der Abhängigkeiten zwischen verschiedenen Parametern, wird für die Modellierung des Einflusses von Ressourcennutzung verwendet und kann unter einigen Annahmen auch in solche Modelle integriert werden. Es werden Regeln für die Übertragung von häufig anzutreffenden Workflow-Mustern, wie Sequenz, paralleler Bearbeitung (AND-Join), Alternativen (XOR- und OR-Join), auf Bayes'sche Netze erarbeitet. Aufgabendauer wird basierend auf einer speziellen Art der Beta-Verteilung, der PERT-Verteilung, modelliert. Es werden Techniken der Diskretisierung dieser Verteilung für die zukünftige Verarbeitung in Bayes'schen Netzen entwickelt und untersucht. Das entworfene Modell wird ergänzt, um zusätzliche Informationen über Ressourcennutzung in Form von Fuzzy-Variablen aufnehmen zu können. Es werden Algorithmen für die Berechnung des Wahrscheinlichkeitsmaßes dieser Variablen ohne und mit A-priori-Informationen über deren Verteilung entwickelt; damit können sie unter Verwendung von virtuellen Evidenzen in Bayes'schen Netzen modelliert werden. Mit diesem Modell ist es möglich, den Einfluss von unsicheren Faktoren auf die Laufzeit von Forschungs- und Entwicklungsprojekten zu messen, Was-wäre-wenn-Szenarien zu erstellen und die Auswirkungen von Änderungen im Projektplan auf dessen Gesamtdauer abzuschätzen.