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Veröffentlichung

"Modeling Microprocessor Faults on High-Level Decision Diagrams", 2nd Workshop on Dependable and Secure Nanocomputing, 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, Anchorage, AK, USA June 24th-27th, 2008

Autoren:
Dr. Jaan Raik
Raimund Ubar
Martin Instenberg
Dr.-Ing. Heinz- Dietrich Wuttke
Typ:
Konferenz
Status:
akzeptiert
Veröffentlichungsdatum
01.06.2008
Abstract:
Automated test generation for digital systems encompasses three activities: selecting a description method, developing a fault model and generating tests to detect the faults covered by the fault model. The efficiency of test generation (quality, speed) is highly depending on the description method and fault models.
As the complexity of digital systems continues to increase, the gate level test generation methods have become
obsolete. Promising approaches are high-level methods. In this paper, a method for describing microprocessors as a special case of digital systems is explained and modeling faults with High-Level Decision Diagrams (HLDD) is presented. HLDDs serve as a basis for a general theory of test generation for mixed-level representations of systems, similarly as we have Boolean algebra for logic-level. HLDDs can be used for representing systems uniformly either at logic-level, high-level or simultaneously at both levels. The fault model on HLDDs represents a generalization of the classical gate-level stuck-at fault model to higher levels - the latter was defined for Boolean expressions whereas the former is defined for nodes in HLDDs having more general interpretation.
Bibtex
Weiterführender Link
http://www2.laas.fr/WDSN08/2ndWDSN08%28LAAS%29_files/WDSN08-Pgm.html
Weiterführendes Dokument
http://www2.laas.fr/WDSN08/2ndWDSN08%28LAAS%29_files/Texts/WDSN08-04-Ubar.pdf