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Veröffentlichung

"Bringing Research Issues into Lab Scenarios on the Example of SOC Testing", ICEE 2007, Coimbra, Portugal, 3 to 7 September 2007.

Autoren:
Raimund Ubar
Artur Jutman
S. Devadse
Dr.-Ing. Heinz- Dietrich Wuttke
Typ:
Konferenz
Status:
akzeptiert
Veröffentlichungsdatum
01.09.2007
Abstract:
Recent reviews have discovered that most VLSI and system designers know little about testing and design for testabilty (DFT) of today’s digital systems because of the gap in education. The importance of test and fault diagnosis as a teaching objective is underestimated in traditional engineering education. Test is usualluy taught as a not very important subtopic in a design course. It is taught as an independent discipline only when it is a hobby horse of a professor. There are two reasons for that: Test is interpreted as a nonproductive issue (vs. design), and the number of courses that should be taught at universities doubles in a decade (Tenhunen, EWME, Lausanne, April 2004).
On the other hand, Test (or Fault Diagnosis) is not only an Electronics Systems related issue, it has an important didactive role for the engineering education in general: a) it is a method to learn how to ask right questions, 2) it develops the ability of analysing cause-effect relationships, and 3) it is looking for answers to the questions like “what is the reason of that what happened?”
Logic world (digital systems) because of its inherent logical complexity could be the best objective for learning the concepts of diagnostic analysis for any technical systems in general. The real targets of education are: creativity, critical thinking, problem solving skills. Therefore, Learning Test at a university should be research oriented.
Bibtex
Weiterführender Link
http://icee2007.dei.uc.pt/index2.htm
Weiterführendes Dokument
http://icee2007.dei.uc.pt/proceedings/papers/429.pdf