The switching and learning behavior of an octopus cell implemented on FPGA. - In: Mathematical biosciences and engineering, ISSN 1551-0018, Bd. 21 (2024), 4, S. 5762-5781
A dendrocentric backpropagation spike timing-dependent plasticity learning rule has been derived based on temporal logic for a single octopus neuron. It receives parallel spike trains and collectively adjusts its synaptic weights in the range [0, 1] during training. After the training phase, it spikes in reaction to event signaling input patterns in sensory streams. The learning and switching behavior of the octopus cell has been implemented in field-programmable gate array (FPGA) hardware. The application in an FPGA is described and the proof of concept for its application in hardware that was obtained by feeding it with spike cochleagrams is given; also, it is verified by performing a comparison with the pre-computed standard software simulation results.
https://doi.org/10.3934/mbe.2024254
Broadband DRA with uniform angular dependent delay for indoor localization. - In: IEEE access, ISSN 2169-3536, Bd. 12 (2024), S. 63644-63654
Estimating the Time Difference of Arrival (TDoA), is a simple yet reliable technique to accurately perform an indoor monostatic localization. To implement TDoA estimation, one approach is to utilize a broadband radar system equipped with multiple receiving antenna elements. To obtain the Time of Arrival (ToA) at each antenna element, the round-trip time is required. However, the round-trip time does not only consist of the propagation delay in free space but the propagation delay within the antenna as well. To perform the localization precisely, it is desired that an antenna element introduces a uniform delay in all directions. To this end, a compact rectangular dielectric resonator antenna is designed for the operating frequency of 6.5 GHz with a fractional bandwidth of 20%. Al2O3 with a dielectric constant of 9.8 is used for the substrate as well as the dielectric resonator. The antenna is designed to provide a high correlation between the input and the output pulses. To investigate the correlation, the antenna is excited with a modulated Gaussian pulse and the radiated pulses are studied. The antenna possesses an excellent behavior in terms of pulse preservation for the upper hemisphere. Therefore, when incoming pulses from the same distance but different directions impinge on the antenna, they reach the port of the antenna at a similar time. It is shown that this feature of the proposed antenna allows the utilization of TDoA estimation without the need for a calibration step. The characteristics of the antenna are verified by simulation and measurement.
https://doi.org/10.1109/ACCESS.2024.3395124
Parallel channel estimation for RIS-assisted Internet of Things. - In: IEEE transactions on intelligent transportation systems, Bd. 0 (2024), 0, S. 1-12
Reconfigurable intelligent surfaces (RISs) are deemed as a potential technique for the future of the Internet of Things (IoT) due to their capability of smartly reconfiguring the wireless propagation environment using a large number of low-cost passive elements. To benefit from RIS technology, the problem of RIS-assisted channel state information (CSI) acquisition needs to be carefully considered. Existing channel estimation methods usually ignored the different channel characteristics of direct channel and reflected channels. In fact, the reflected channel can be smartly configured by adjusting the phase shifts of the RIS, which is different from the direct channel due to the different path loss exponents between the transmitter and receiver. Therefore, it is necessary to further develop a RIS-assisted channel estimation to determine the direct and reflected channels, respectively. In this paper, we study a RIS-assisted channel estimation that jointly exploits the properties of the direct and the reflected channel to provide more accurate CSI. The direct channel is estimated using weighted ℓ1 norm minimization, while the reflected channel is modeled based upon the robust ℓ1,τ norm minimization to sequentially estimate the channel parameters. Moreover, by combining the gradient descent and the alternating minimization method, a flexible and fast algorithm is developed to provide a feasible solution. Simulation results demonstrate that an RIS-aided MIMO system significantly reduces the active antennas/RF chains compared to other benchmark schemes.
https://doi.org/10.1109/TITS.2024.3364248
Joint radar and communications: architectures, use cases, aspects of radio access, signal processing, and hardware. - In: IEEE access, ISSN 2169-3536, Bd. 12 (2024), S. 47888-47914
Joint Radar and Communications (JRC) can satisfy the apparent demand for applications based on object detection, tracking, ranging, and positioning. JRC is, therefore, often seen as candidate technology for 6G mobile systems. Implementing JRC will require novel approaches in many research and engineering fields, including protocol design, digital and analog signal processing, and hardware development. The ongoing debates on JRC already include many white papers and research articles ranging in content from very specific technical problems to comprehensive bird’s eye-level reviews. This paper represents the work within the Open6GHub research project in Germany, which aims to investigate and implement potential end-to-end solutions for 6G. In this framework, we propose a consolidated vision for potential JRC architectural approaches. The subsequent discussion on integrating radar sensing with communications highlights this technology’s state-of-the-art and presents relevant opportunities and challenges.
https://doi.org/10.1109/ACCESS.2024.3383771
Precoding design and PMI selection for BICM-MIMO systems with 5G New Radio type-I CSI. - In: IEEE transactions on communications, ISSN 1558-0857, Bd. 0 (2024), 0, S. 1-15
This paper proposes novel linear precoding algorithms for Multiple-Input Multiple-Output Bit-Interleaved Coded Modulation (MIMO-BICM) systems that maximize the achievable rate subject to power constraints. To overcome the nonlinear and nonconvex nature of the optimization problem, we rewrite the achievable rate in terms of the log-likelihood ratio (LLR) and introduce manifold-based gradient ascent (MGA) precoding and low-complexity non-iterative algorithms. Simulation results show significant gains in achievable rate and block error rate compared to existing techniques. Additionally, we extend our investigation to linear precoding with the constraint that the precoding matrix is selected from the codebook type-I adopted in Fifth-Generation New Radio (5G NR) networks. We propose heuristic algorithms that exploit the Kronecker and Discrete Fourier Transform (DFT) structure of the codebook and consider the singular vector decomposition (SVD) precoder as the optimal reference precoder. The traditional exhaustive search methods require a high complexity, especially for large codebook sizes. However, our proposed algorithms apply a combination of direct estimation and a low-dimensional search for deriving the indices, resulting in a reduced number of codebook precoder candidates. Simulation results show that our proposed low-complexity algorithms perform comparably to exhaustive search baselines.
https://doi.org/10.1109/TCOMM.2024.3383106
Electrical simulations of the SIS100 superconducting dipole and quadrupole circuits: transients, earthing and failure modes. - In: IEEE transactions on applied superconductivity, ISSN 1558-2515, Bd. 34 (2024), 5, 4903805, insges. 5 S.
The 100 Tm superconducting synchrotron SIS100 is the main accelerator of the international Facility for Antiproton and Ion Research (FAIR) currently under advanced construction in Darmstadt, Germany. The SIS100 dipole circuit which creates the magnetic field required to bend the beam, consists of 108 dipoles distributed over six arc sections of the ring. The magnetic field for the beam focusing is generated by three individual quadrupole circuits with total amount of 166 magnets located in both arc and straight sections of the ring. The dipole circuit is powered from two synchronized power converters and will be cycled up to 13.2 kA at 28 kA/s. The dipole magnet chain is not self-protecting. 12 energy extraction resistors are used to protect the superconducting coils and bus-bars against overheating and overvoltage in case of a quench. The largest quadrupole circuit consists of 83 magnets. The nominal current is 10.5 kA cycled up to 22 kA/s. Similarly to dipoles, the quadrupole circuit is not self-protecting. Four energy extraction units are used to discharge the circuit's energy in case of a quench or fast power abort. This work presents a customized Python software tool created to simulate electrical behavior of a superconducting magnet chain. The software is under development at GSI. However, certain modules strongly rely on the approach developed at CERN. The paper contains selected simulations of the SIS100 dipole and defocusing quadrupole circuits. Special attention is drawn to: transient effects during typical operation and during the fast power abort; the damping effect of vacuum chambers; voltage distribution in the circuits and basic failure modes.
https://doi.org/10.1109/TASC.2024.3375293
Short- and long-term state switching in the superconducting niobium neuron plasticity. - In: IEEE transactions on applied superconductivity, ISSN 1558-2515, Bd. 34 (2024), 3, 1300105, insges. 5 S.
Bio-inspired algorithms and architectures are considered superior to classical architectures for certain applications. An important aspect with regard to the function of the human memory is the sorting according to important and unimportant experiences. Certain important experiences are stored significantly longer than less important ones. One criterion to make this distinction is the frequency of occurrence of a property. In this work an RSFQ circuit is presented, which performs this weighting in the learning process of a synapse. In a simulation study, the principle of the selective learning mechanism is shown to work and a variant of permanent memory is demonstrated.
https://doi.org/10.1109/TASC.2024.3355876
Wafer-scale Al junction technology for superconducting quantum circuits. - In: IEEE transactions on applied superconductivity, ISSN 1558-2515, Bd. 34 (2024), 3, 1701005, insges. 5 S.
Josephson tunnel junctions represent a key element in superconducting electronics and quantum circuits. For many years, shadow evaporation by means of Dolan-type bridges has been the state-of-the-art for deep sub- micrometer sized structures. Increasing demand in the number of Josephson junctions, e.g., in qubit circuits and travelling wave parametric amplifiers, requests for a wafer-scale fabrication process with precise control of junction parameters and have led to an advanced lift-off technique called Manhattan-type junction technology in recent years. Herein, we report on the development of a 100 mm wafer-scale fabrication technology for deep sub-micrometer sized Al Josephson junctions with linear dimensions down to 180 nm. The critical current IC of the junctions ranges from about 10 to 120 nA scaling with their linear dimensions. Low temperature transport measurements as well as room-temperature characterization has been used for IC and process homogeneity determination of series arrays of up to 50 Josephson junctions. We discuss technology parameters such as yield, on-chip and on-wafer reproducibility of the junction's critical currents as well as main process limitations. Moreover, we present experimental results on the characterization of first transmon-type qubits fabricated using this technology.
https://doi.org/10.1109/TASC.2024.3350580
Towards fabrication of sub-micrometer cross-type aluminum Josephson junctions. - In: IEEE transactions on applied superconductivity, ISSN 1558-2515, Bd. 34 (2024), 3, 1101205, insges. 5 S.
The performance of superconducting electronic devices such as superconducting quantum bits (qubits) and superconducting quantum interference devices (SQUIDs) strongly relies on high-quality Josephson junctions (JJ) and their integration into surrounding circuit elements. Therefore, a corresponding fabrication technology should allow for the fabrication of all required elements including the JJs, inductances, capacitances and waveguides. For a long time, shadow evaporation technique was the state of the art for the implementation of sub-µm sized JJs based on aluminum for qubits of high coherence times. Although, the use of a single lithographic step represents a major advantage of this technique. However, shadowing effects limit sample size, device complexity, and thus scalability of the circuitry. To overcome these limitations and to meet the demands of next generation scalable quantum circuits, in this work we introduce our cross-type JJ aluminum technology, where JJs are defined by the overlap of two narrow perpendicular stripes. We discuss the technological challenges, with a focus on our newly developed dry etching process for patterning of the aluminum thin film. Compared to a lift-off based process, this advanced wafer-scale fabrication technology offers a high integration density and the required design flexibility. We will present first results on cross-type aluminum JJs.
https://doi.org/10.1109/TASC.2023.3343681
Advanced FLUXONICS process CJ2 based on sub-µm-sized cross-type Nb/AlOx/Nb Josephson junctions for mixed signal circuits. - In: IEEE transactions on applied superconductivity, ISSN 1558-2515, Bd. 34 (2024), 3, 1101105, insges. 5 S.
Quantum computers represent a prominent example of technology harnessing quantum phenomena for practical applications. Implementations based on superconducting solid-state qubits play a leading role. These have facilitated the implementation of the first commercially viable quantum computers through the use of well-established and scalable fabrication technologies. As the number of qubits in these systems is continuously increasing, there is an urgent need to advance wiring and integration methods. Specifically, the demand for high-frequency control and readout lines within the millikelvin coolers introduces unwanted heat load. As a scalable alternative, superconducting digital electronics has been proposed as a promising candidate for direct interfacing with superconducting quantum circuits. We, therefore, advanced our well-established cross-type, sub-micrometer-sized Nb-based Josephson junction technology for analog circuits to allow for the implementation of digital circuits. Thus, an advanced mixed signal process CJ2 hosts both, analog and digital circuits, on a single chip, using Josephson junctions of a wide critical current range. We discuss the technology and the realization of first circuits as well as results of basic logic gate and dc-SQUID operations. This advanced technology CJ2 enables the development of digital interfaces for quantum circuits by academic and industrial partners in the framework of the European FLUXONICS foundry.
https://doi.org/10.1109/TASC.2024.3355024