Research

The massive computing power required to train and deploy next-generation Artificial Intelligence (AI) systems and Large Language Models (LLMs) has triggered a critical demand for specialized, high-performance integrated circuits (ICs). However, traditional IC design flows are increasingly unable to keep pace with the growing complexity, scale, and time-to-market requirements of AI circuits and systems, which require hardware architectures that are highly adaptive, energy-efficient, and optimized across multiple levels of abstraction.

 

To address these challenges, our research group focuses on leveraging state-of-the-art AI technologies to design the next generation of AI-capable chips, moving beyond traditional manual, script-driven chip design workflows toward intelligent and autonomous engineering environments. In particular, our research integrates advances in machine learning, generative AI, design automation, and hardware–software co-optimization to address key bottlenecks in modern chip design. Our research topics are summarized as follows:

ReKI

RTL Code Generation & Optimization: Generating hardware description code (Verilog/VHDL) from natural language specifications is a foundational step in automated chip design. Our objective is to eliminate the structural hallucinations in LLMs and ensure synthesis-ready circuit descriptions by developing advanced pre-filtering, post-ranking, and focused reasoning frameworks.

Automated Verification & Testbench Construction: Circuit verification consumes over 70% of the entire chip design cycle. We address this bottleneck by engineering intelligent, closed-loop self-correction environments that separate simulation stimuli from high-level checking logic, utilizing live simulator error logs to build self-debugging systems that autonomously isolate, trace, and resolve issues in hardware design.

High-Level Synthesis (HLS) Refinement: High-Level Synthesis (HLS) compiles algorithmic software languages (C/C++) directly into hardware descriptions to reduce time-to-market. We work on AI-driven, automated code-refactoring procedures that automatically repair un-synthesizable code structures in HLS, validate behavioral discrepancies through differential testing, and intelligently optimize compilation pragmas and bit-widths to unlock superior Power, Performance, and Area (PPA) metrics of chip design.

AI-driven Computer Architecture: The ability of state-of-the-art AI tools in exploring large design space of integrated circuits and computer architecture also provides opportunities for new chip design and computing solutions. We work on new formulations of computing with digital circuits and leverage AI tools to derive resource-efficient computer architecture for AI applications.