Master thesis
1. Early Error Localization in LLM-Generated Verilog Using Pyverilog/LLM
Introduction: This project investigates LLM-assisted Verilog code generation and verification, with a focus on early error localization in LLM-generated Verilog. It combines a review of LLMs for EDA and functional error detection methods with practical exploration of Pyverilog-based AST, dataflow, and control-flow analysis, aiming to detect, narrow down, and localize potential errors without relying on a testbench.
Suitable for: Bachelor / Master
Supervisor: M.Sc. Wen Bing
Contact: wen.bing@tu-ilmenau.de
2. Mugica: Mutation-guided Automatic Testbench Generation
Introduction: This research investigates how mutation testing can actively guide the automatic generation of testbenches for RTL hardware designs, leveraging large language models (LLMs) to translate mutant-killing objectives into concrete stimulus and checker generation. The work includes designing hardware-specific mutation operators, developing LLM-based strategies to generate and iteratively refine testbench components in response to surviving mutants, and building a feedback loop that drives the process until a satisfactory mutation score is achieved. Practical challenges such as equivalent mutant detection, prompt engineering for hardware contexts, and simulation cost reduction will also be addressed.
Suitable for: Master
Supervisor: M.Sc. Jiajun Wu
Contact: jiajun.wu@tu-ilmenau.de
Bachelor thesis
1. Double-Buffer-Aware Weight-Stationary Systolic Array for Resource-Efficient Neural Network Inference on ARM-FPGA Edge Platforms
Introduction: This thesis investigates the design of a resource-efficient neural network accelerator on an ARM-FPGA edge platform. The core innovation is a double-buffer-aware weight-stationary systolic array architecture, where weights are kept inside processing elements to improve data reuse, while double buffering is used to overlap data transfer and computation. The expected work includes designing the systolic array, implementing input/weight/output buffers, integrating the accelerator with the ARM processor through an AXI-based interface, and evaluating inference latency, throughput, resource utilization, and speedup compared with ARM-only execution and a baseline MAC-array accelerator. This topic extends the original ARM-FPGA neural network accelerator project, which already focuses on ARM control, FPGA computation modules, buffers, MAC arrays, AXI communication, and performance comparison.
Suitable for: Bachelor
Supervisor: M.Sc. Hengjun Liu
Contact: hengjun.liu@tu-ilmenau.de
2. An Automated Harness Framework for HDL Generation
Introduction: While AI code generation works exceptionally well for software, it struggles with hardware design because Hardware Description Languages (HDLs) like Verilog lack unified testing environments and automated feedback loops. This project explores the feasibility of an automated framework—an HDL harness—specifically designed for AI-driven hardware generation. You will build an evaluation environment where a Large Language Model (LLM) can autonomously design, test, and refine hardware components. The core of this project involves developing a middleware framework that bridges traditional, rigid Electronic Design Automation (EDA) simulation tools with flexible, LLM-compatible interfaces, enabling a seamless "AI-in-the-loop" hardware engineering pipeline.
Suitable for: Bachelor
Supervisor: M.Sc. Shengchao Zhang
Contact: shengchao.zhang@tu-ilmenau.de
Group studies
1. An Automated Harness Framework for HDL Generation
Introduction: This project focuses on the design and implementation of a hybrid neural network accelerator that combines a simulated RRAM-based analog computing subsystem with digital computing hardware. The RRAM subsystem will be represented by a software-based simulation model, so no physical RRAM device is required. The model will reproduce the main behavior of RRAM-based in-memory computing and can include configurable non-ideal effects, such as computation errors caused by device variations.
The primary goal of this project is to develop a digital MAC array, such as a systolic array, and integrate it with the simulated RRAM subsystem. Neural network computations that are sensitive to analog errors can be executed on the digital MAC array, while suitable computations can be evaluated using the RRAM model. The project will also investigate configurable dataflow and computation precision, as well as the control and data exchange mechanisms required to coordinate the two computing domains. The final demonstration will execute a lightweight neural network and evaluate the hybrid system in terms of accuracy, throughput, latency, and hardware resource usage.
Suitable for: Master
Supervisor: M.Sc. Hengjun Liu, M.Sc. Xinyu Wei
Contact: hengjun.liu@tu-ilmenau.de, xinyu.wei@tu-ilmenau.de
Research projects
1. The Area Cost of Learned Execution: A Neural Model of the Intel 8080 Against an RTL Reference
Introduction: Neural networks can theoretically represent arbitrary computation, but the hardware cost of doing so remains unclear. The Intel 8080 provides a suitable case study because its ISA is small and well documented, reference simulators and validation programs are available, and a synthesisable RTL implementation can serve as a baseline. This project compares a conventional RTL implementation with a learned neural approximation of the same instruction-level state-transition function on the same FPGA platform.
Suitable for: Master
Supervisor: M.Sc. Xinyu Wei
Contact: xinyu.wei@tu-ilmenau.de
2. Generating Sequential Logic Circuits from State-Transition Tables Using Search Algorithms
Introduction: The goal of this project is straightforward: given a state-transition table, automatically generate a sequential logic circuit that implements it correctly and uses as few logic gates as possible. The generated circuit will use only two-input NAND gates and D flip-flops (DFFs). DFFs store the circuit state, while NAND gates compute the next state and output signals.
Suitable for: Master
Supervisor: M.Sc. Hengjun Liu
Contact: hengjun.liu@tu-ilmenau.de
3. SpecOrder: Requirement Order Sensitivity and Dependency-Aware Canonicalization for LLM-Based RTL Generation
Introduction: The order of requirements in natural-language hardware specifications may influence the quality of RTL generated by Large Language Models (LLMs). This project investigates how different requirement orderings affect Verilog generation and functional correctness. By identifying logical dependencies between requirements, the project aims to develop a dependency-aware reordering approach that improves the accuracy and robustness of LLM-based RTL generation.
Suitable for: Master
Supervisor: M.Sc. Wen Bing
Contact: wen.bing@tu-ilmenau.de
