Master thesis
1. Early Error Localization in LLM-Generated Verilog Using Pyverilog/LLM
Introduction:This project investigates LLM-assisted Verilog code generation and verification, with a focus on early error localization in LLM-generated Verilog. It combines a review of LLMs for EDA and functional error detection methods with practical exploration of Pyverilog-based AST, dataflow, and control-flow analysis, aiming to detect, narrow down, and localize potential errors without relying on a testbench.
Suitable for: Bachelor / Master
Supervisor: M.Sc. Wen Bing
Contact: wen.bing@tu-ilmenau.de
2. Mugica: Mutation-guided Automatic Testbench Generation
Introduction: This research investigates how mutation testing can actively guide the automatic generation of testbenches for RTL hardware designs, leveraging large language models (LLMs) to translate mutant-killing objectives into concrete stimulus and checker generation. The work includes designing hardware-specific mutation operators, developing LLM-based strategies to generate and iteratively refine testbench components in response to surviving mutants, and building a feedback loop that drives the process until a satisfactory mutation score is achieved. Practical challenges such as equivalent mutant detection, prompt engineering for hardware contexts, and simulation cost reduction will also be addressed.
Suitable for: Master
Supervisor: M.Sc. Jiajun Wu
Contact: jiajun.wu@tu-ilmenau.de
Bachelor thesis
1. Double-Buffer-Aware Weight-Stationary Systolic Array for Resource-Efficient Neural Network Inference on ARM-FPGA Edge Platforms
Introduction:This thesis investigates the design of a resource-efficient neural network accelerator on an ARM-FPGA edge platform. The core innovation is a double-buffer-aware weight-stationary systolic array architecture, where weights are kept inside processing elements to improve data reuse, while double buffering is used to overlap data transfer and computation. The expected work includes designing the systolic array, implementing input/weight/output buffers, integrating the accelerator with the ARM processor through an AXI-based interface, and evaluating inference latency, throughput, resource utilization, and speedup compared with ARM-only execution and a baseline MAC-array accelerator. This topic extends the original ARM-FPGA neural network accelerator project, which already focuses on ARM control, FPGA computation modules, buffers, MAC arrays, AXI communication, and performance comparison.
Suitable for: Bachelor
Supervisor: M.Sc. Hengjun Liu
Contact: hengjun.liu@tu-ilmenau.de
2. An Automated Harness Framework for HDL Generation
Introduction:While AI code generation works exceptionally well for software, it struggles with hardware design because Hardware Description Languages (HDLs) like Verilog lack unified testing environments and automated feedback loops. This project explores the feasibility of an automated framework—an HDL harness—specifically designed for AI-driven hardware generation. You will build an evaluation environment where a Large Language Model (LLM) can autonomously design, test, and refine hardware components. The core of this project involves developing a middleware framework that bridges traditional, rigid Electronic Design Automation (EDA) simulation tools with flexible, LLM-compatible interfaces, enabling a seamless "AI-in-the-loop" hardware engineering pipeline.
Suitable for: Bachelor
Supervisor: M.Sc. Shengchao Zhang
Contact: shengchao.zhang@tu-ilmenau.de
Group studies
No topics available.
Research projects
No topics available.
