Publikationen an der Fakultät für Informatik und Automatisierung ab 2015

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Kläbe, Steffen; Sattler, Kai-Uwe; Baumann, Stephan;
PatchIndex: exploiting approximate constraints in distributed databases. - In: Distributed and parallel databases : an international journal.. - New York, NY [u.a.] : Consultants Bureau, ISSN 1573-7578, Bd. 39 (2021), 3, S. 833-853

Cloud data warehouse systems lower the barrier to access data analytics. These applications often lack a database administrator and integrate data from various sources, potentially leading to data not satisfying strict constraints. Automatic schema optimization in self-managing databases is difficult in these environments without prior data cleaning steps. In this paper, we focus on constraint discovery as a subtask of schema optimization. Perfect constraints might not exist in these unclean datasets due to a small set of values violating the constraints. Therefore, we introduce the concept of a generic PatchIndex structure, which handles exceptions to given constraints and enables database systems to define these approximate constraints. We apply the concept to the environment of distributed databases, providing parallel index creation approaches and optimization techniques for parallel queries using PatchIndexes. Furthermore, we describe heuristics for automatic discovery of PatchIndex candidate columns and prove the performance benefit of using PatchIndexes in our evaluation.
Hunold, Alexander; Haueisen, Jens; Freitag, Christine M.; Siniatchkin, Mikhail; Moliadze, Vera;
Cortical current density magnitudes during transcranial direct current stimulation correlate with skull thickness in children, adolescent and young adults. - In: Non-invasive brain stimulation (NIBS) in neurodevelopmental disorders. - Amsterdam : Elsevier, (2021), S. 41-56

Transcranial direct current stimulation protocols are often applied with a fixed parameter set to all subjects participating in an interventional study. This might lead to considerable effect variation in inhomogeneous subject groups or when transferring stimulation protocols to different age groups. The aim of this study was to evaluate magnitude differences of the electric current density distribution on the gray matter surface in children, adolescent and adults in correlation with the individual volume conductor geometry. We generated individual six compartment finite element models from structural magnetic resonance images of four children (age: 10.95 a±1.32 a), eight adolescents (age: 15.10 a±1.16 a) and eight young adults (age: 21.62 a±2.45 a). We determined the skull thickness in the models as Euclidean distance between the surface of the cerebrospinal fluid compartment and outer skull boundary. For tDCS simulations, we modeled 5×7cm patch electrodes impressing 1mA current intensity as anode and cathode over the left M1 and the right fronto-polar orbit, respectively. The resulting current density was analyzed on the gray matter surface. Our results demonstrate higher cortical current density magnitudes in children compared to adults for a given tDCS current strength. Above the evaluated cortex, the skull thickness increased with age. In conclusion, we underline the importance of age-dependent and individual models in tDCS simulations.

Rabe, Martin; Milz, Stefan; Mäder, Patrick;
Development methodologies for safety critical machine learning applications in the automotive domain: a survey. - In: IEEE Xplore digital library. - New York, NY : IEEE, ISSN 2473-2001, (2021), S. 129-141

Enabled by recent advances in the field of machine learning, the automotive industry pushes towards automated driving. The development of traditional safety-critical automotive software is subject to rigorous processes, ensuring its dependability while decreasing the probability of failures. However, the development and training of machine learning applications substantially differs from traditional software development. The processes and methodologies traditionally prescribed are unfit to account for specifics like, e.g., the importance of datasets for a development. We perform a systematic mapping study surveying methodologies proposed for the development of machine learning applications in the automotive domain. We map the identified primary publications to a general machine learning-based development process and preliminary assess their maturity. The reviewss goal is providing a holistic view of current and previous research contributing to ML-aware development processes and identifying challenges that need more attention. Additionally, we list methods, network architectures, and datasets used within these publications. Our meta-study identifies that model training and model V&V received by far the most research attention accompanied by the most mature evaluations. The remaining development phases, concerning domain specification, data management, and model integration, appear underrepresented and in need of more thorough research. Additionally, we identify and aggregate typically methods applied when developing automated driving applications like models, datasets and simulators showing the state of practice in this field.
Hunold, Alexander;
Transcranial electric stimulation : modeling, application, verification. - Ilmenau : Universitätsbibliothek, 2021. - 1 Online-Ressource (verschiedene Seitenzählungen).
Technische Universität Ilmenau, Dissertation 2021

Die Verwendung von Elektrizität zur Beeinflussung neuronaler Aktivität weckte das Interesse neurowissenschaftlicher Forschung und zeigt bereits seit einigen Jahrhunderten therapeutische Wirkungen. In den letzten Jahrzehnten fand die nicht-invasive Anwendung schwacher Ströme von wenigen Milliampere am Kopf, bezeichnet als transkranielle Elektrostimulation (tES), in den Neurowissenschaften und der klinischen Forschung vielfältige Anwendungen. Die konventionell aufwendige implementierte Elektrodenschnittstelle und eher unspezifische Verteilung der Stimulationsströme benötigen jedoch weitere Innovationen und Verifikationen. Die vorliegende Arbeit befasst sich mit der Modellierung des Stromflusses für die gezielte Elektrostimulation, mit der Entwicklung von Elektrodenkonzepten für die Stromeinprägung, sowie mit mess-technischen Ansätzen zur Verifikation von Stimulationskonfigurationen. Simulationen transorbitaler Stromstimulationen zeigten Stromdichteverteilungen in der Netzhaut, die in Abhängigkeit von der Elektrodenmontage deutlich unterschiedliche lokale Maxima aufwiesen. In ähnlicher Weise wurden orts- und orientierungsspezifische Ziele im Kortex mit Simulationen von Konfigurationen mehrerer Elektroden auf dem Kopf adressiert. Diese Simulationen zeigten die Realisierbarkeit zielgenauer Stimulationskonfigurationen für die Retina und Zielgebiete im Kortex. Für die Stimulationsanwendung wurden neue Konzepte auf Basis von textilen Elektroden mit integriertem Elektrolytreservoir und gedruckten Trockenelektroden eingeführt, die in flexiblen Hauben eingearbeitet sind. Diese neu entwickelten Elektroden zeigten ihre Funktionalität in Studien, die zuvor beschriebenen Effekte der Stromstimulation reproduzierten, wobei sie die Präzision und Reproduzierbarkeit der Stimulation erhöhten und den Vorbereitungsaufwand verringerten. Für technische Verifikationsexperimente wurden ein homogener Volumenleiter und ein realistisch geformtes dreischichtiges Kopfphantom physikalisch realisiert. Messtechnische Experimente an diesen Phantomen zeigten die Machbarkeit von Stimulationskonfigurationen mit mehreren Elektroden, insbesondere den Ansatz der zeitlichen Interferenz, und verifizierten die Stabilität der neuen Elektrodenkonzepte. Zusammenfassend trägt die vorliegende Arbeit zu Innovationen auf dem Gebiet der tES bei, indem ein neuer Multi-Elektroden-Ansatz für die Adressierung kortikaler Ziele, neuen angepassten Elektrodenkonzepte und physikalische Phantome für die metrologische Verifikation beschrieben werden.
Irmak, Hasan; Corradi, Federico; Detterer, Paul; Alachiotis, Nikolaos; Ziener, Daniel;
A dynamic reconfigurable architecture for hybrid spiking and convolutional FPGA-based neural network designs. - In: Journal of Low Power Electronics and Applications : open access journal.. - Basel : MDPI, ISSN 2079-9268, Bd. 11 (2021), 3, S. 1-25

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.
Asghar, Ali; Hettwer, Benjamin; Karimov, Emil; Ziener, Daniel;
Increasing side-channel resistance by netlist randomization and FPGA-based reconfiguration. - In: Applied Reconfigurable Computing. Architectures, Tools, and Applications. - Cham : Springer International Publishing, (2021), S. 173-187

Modern FPGAs are equipped with the possibility of Partial Reconfiguration (PR) which along with other benefits can be used to enhance the security of cryptographic implementations. This feature requires development of alternative designs to be exchanged during run-time. In this work, we propose dynamically alterable circuits by exploring netlist randomization which can be utilized with PR as a countermeasure against physical attacks, in particular side-channel attacks. The proposed approach involves modification of an AES implementation at the netlist level in order to create circuit variants which are functionally identical but structurally different. In preliminary experiments, power traces of these variants have been shuffled to replicate the effect of partial reconfiguration. With these dynamic circuits, our experimental results show an increase in the resistance against power side-channel attacks by a factor of [Tilde] 12.6 on a Xilinx ZYNQ UltraScale+ device.

Schatz, David; Roßberg, Michael; Schäfer, Günter;
Optimizing packet scheduling and path selection for anonymous voice calls. - In: The ACM digital library. - New York, NY : ACM, (2021), insges. 10 S.

Onion routing is a promising approach to implement anonymous voice calls. Uniform-sized voice packets are routed via multiple relays and encrypted in layers to avoid a correlation of packet content in different parts in the network. By using pre-built circuits, onion encryption may use efficient symmetric ciphers. However, if packets are forwarded by relays as fast as possible - to minimize end-to-end latency - network flow watermarking may still de-anonymize users. A recently proposed countermeasure synchronizes the start time of many calls and batch processes voice packets with the same sequence number in relays. However, if only a single link with high latency is used, it will also negatively affect latency of all other calls. This article explores the limits of this approach by formulating a mixed integer linear program (MILP) that minimizes latency "bottlenecks" in path selection. Furthermore, we suggest a different scheduling strategy for voice packets, i.e. implementing independent de-jitter buffers for all flows. In this case, a MILP is used to minimize the average latency of selected paths. For comparison, we solve the MILPs using latency and bandwidth datasets obtained from the Tor network. Our results show that batch processing cannot reliably achieve acceptable end-to-end latency (below 400 ms) in such a scenario, where link latencies are too heterogeneous. In contrast, when using de-jitter buffers for packet scheduling, path selection benefits from low latency links without degrading anonymity. Consequently, acceptable end-to-end latency is possible for a large majority of calls.
Kuske, Dietrich;
Second-order finite automata: expressive power and simple proofs using automatic structures. - Cham : Springer. - 1 Online-Ressource (Seite 242-254).

Second-order finite automata, introduced recently by Andrade de Melo and de Oliveira Oliveira, represent classes of languages. Since their semantics is defined by a synchronized rational relation, they can be studied using the theory of automatic structures. We exploit this connection to uniformly reprove and strengthen known and new results regarding closure and decidability properties concerning these automata. We then proceed to characterize their expressive power in terms of automatic classes of languages studied by Jain, Luo, and Stephan.
Schlegel, Marius;
Poster: Shielding AppSPEAR - enhancing memory safety for trusted application-level security policy enforcement. - In: The ACM digital library. - New York, NY : ACM, (2021), S. 99-101

This paper tackles the problem of memory-safe implementation of the AppSPEAR framework for application-level security policy enforcement. We contribute with a feasibility study that demonstrates the performance overhead of applying Rust's memory safety features on top of SGX trusted execution technology.
Lasch, Robert; Schulze, Robert; Legler, Thomas; Sattler, Kai-Uwe;
Workload-driven placement of column-store data structures on DRAM and NVM. - In: The ACM digital library. - New York, NY : ACM, (2021), insges. 8 S.

Non-volatile memory (NVM) offers lower costs per capacity and higher total capacities than DRAM. However, NVM cannot simply be used as a drop-in replacement for DRAM in database management systems due to its different performance characteristics. We thus investigate the placement of column-store data structures in a hybrid hierarchy of DRAM and NVM, with the goal of placing as much data as possible in NVM without compromising performance. After analyzing how different memory access patterns affect query runtimes when columns are placed in NVM, we propose a heuristic that leverages lightweight access counters to suggest which structures should be placed in DRAM and which in NVM. Our evaluation using TPC-H shows that more than 80% of the data touched by queries can be placed in NVM with almost no slowdown, while naively placing all data in NVM would increase runtime by 53%.