3D INS/UWB based real time sensor fusion indoor position tracking architecture. - In: IEEE Xplore digital library, ISSN 2473-2001, (2022), S. 94-101
Accurate indoor position tracking and analysis of the movement dynamics of autonomous driving systems are important challenges when it comes to automatize industrial processing, supply chains or warehouses. In this paper, the authors present an indoor position tracking architecture with a novel sensor fusion approach for autonomous robots in three-dimensional space. For robots to be able to drive autonomous, they need information of their position, speed and orientation in 3D-space. With the presented architecture, position information is provided by the Indoor Positioning System (IPS) and orientation information as well as velocity are determined by the Inertial Navigation System (INS). The proposed tracking architecture combines those informations with a sensor fusion approach, thus enabling the autonomous driving system.
The benefits and costs of netlist randomization based side-channel countermeasures: an in-depth evaluation. - In: Journal of Low Power Electronics and Applications, ISSN 2079-9268, Bd. 12 (2022), 3, 42, S. 1-17
Exchanging FPGA-based implementations of cryptographic algorithms during run-time using netlist randomized versions has been introduced recently as a unique countermeasure against side channel attacks. Using partial reconfiguration, it is possible to shuffle between structurally different but functionally similar versions of a cryptographic implementation. The resulting varying power profile enhances the resistance against power-based side channel attacks. While side channel leakage is reduced, costs in terms of additional resources and/or lowered throughput are often increased due to the overheads of the required online partial reconfiguration. In this work, we provide an in-depth evaluation of the leakage-area-throughput trade-off.
Security by Reconfiguration (SecRec) - Physikalische Sicherheit durch dynamische Hardware-Rekonfiguration, Teilvorhaben: Schutz vor Reverse-Engineering und Fehlerinjektionsangriffen durch dynamische Hardware-Rekonfiguartion : Abschlussbericht : Projektstart: 1. Januar 2017, Laufzeit: 48 Monate : Berichtszeitraum: 1. Januar 2017-30. September 2020. - Ilmenau : [Technische Universität Ilmenau]. - 1 Online-Ressource (17 Seiten, 390,27 KB)Förderkennzeichen BMBF 16KIS0609
Increasing flexibility of FPGA-based CNN accelerators with dynamic partial reconfiguration. - In: 2021 31st International Conference on Field-Programmable Logic and Applications, (2021), S. 306-311
Convolutional Neural Networks (CNN) are widely used for image classification and have achieved significantly accurate performance in the last decade. However, they require computationally intensive operations for embedded applications. In recent years, FPGA-based CNN accelerators have been proposed to improve energy efficiency and throughput. While dynamic partial reconfiguration (DPR) is increasingly used in CNN accelerators, the performance of dynamically reconfigurable accelerators is usually lower than the performance of pure static FPGA designs. This work presents a dynamically reconfigurable CNN accelerator architecture that does not sacrifice throughput performance or classification accuracy. The proposed accelerator is composed of reconfigurable macroblocks and dynamically utilizes the device resources according to model parameters. Moreover, we devise a novel approach, to the best of our knowledge, to hide the computations of the pooling layers inside the convolutional layers, thereby further improving throughput. Using the proposed architecture and DPR, different CNN architectures can be realized on the same FPGA with optimized throughput and accuracy. The proposed architecture is evaluated by implementing two different LeNet CNN models trained by different datasets and classifying different classes. Experimental results show that the implemented design achieves higher throughput than current LeNet FPGA accelerators.
KOI: an architecture and framework for industrial and academic machine learning applications. - In: Modelling and development of intelligent systems, (2021), S. 113-128
A dynamic reconfigurable architecture for hybrid spiking and convolutional FPGA-based neural network designs. - In: Journal of Low Power Electronics and Applications, ISSN 2079-9268, Bd. 11 (2021), 3, 32, insges. 25 S.
This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.
Increasing side-channel resistance by netlist randomization and FPGA-based reconfiguration. - In: Applied reconfigurable computing, (2021), S. 173-187
Modern FPGAs are equipped with the possibility of Partial Reconfiguration (PR) which along with other benefits can be used to enhance the security of cryptographic implementations. This feature requires development of alternative designs to be exchanged during run-time. In this work, we propose dynamically alterable circuits by exploring netlist randomization which can be utilized with PR as a countermeasure against physical attacks, in particular side-channel attacks. The proposed approach involves modification of an AES implementation at the netlist level in order to create circuit variants which are functionally identical but structurally different. In preliminary experiments, power traces of these variants have been shuffled to replicate the effect of partial reconfiguration. With these dynamic circuits, our experimental results show an increase in the resistance against power side-channel attacks by a factor of [Tilde] 12.6 on a Xilinx ZYNQ UltraScale+ device.
An energy-efficient FPGA-based convolutional neural network implementation. - In: S&ptbov;IU 2021, (2021), insges. 4 S.
Convolutional Neural Networks (CNNs) are a very popular class of artificial neural networks. Current CNN models provide remarkable performance and accuracy in image processing applications. However, their computational complexity and memory requirements are discouraging for embedded realtime applications. This paper proposes a highly optimized CNN accelerator for FPGA platforms. The accelerator is designed as a LeNet CNN architecture focusing on minimizing resource usage and power consumption. Moreover, the proposed accelerator shows more than 2x higher throughput in comparison with other FPGA LeNet accelerators with reaching up 14 K images/sec. The proposed accelerator is implemented on the Nexys DDR 4 board and the power consumption is less than 700 mW which is 3x lower than the current LeNet architectures. Therefore, the proposed solution offers higher energy efficiency without sacrificing the throughput of the CNN.
A complete open source design flow for Gowin FPGAs. - In: 2020 International Conference on Field-Programmable Technology, (2020), S. 182-189
In this paper, we propose an open source design flow for the low cost FPGAs from the company Gowin. Open source design tools are opening the door for custom extensions and modification in the design flow. The proposed design flow which supports almost all Gowin FPGA resources, is based on well-known open source tools, like Yosys and nextpnr, as well as on our proposed open source bitstream generator. The necessary architectural details of the FPGA family are gathered by input fuzzing and comparisons with the vendor tool flow. Experimental results show an almost similar performance as the vendor tools.
A resource-saving approach for adding redundancy to a Network-on-Chip system. - In: 2020 IEEE 44th Annual Computers, Software, and Applications Conference, (2020), S. 1417-1422
FPGAs (Field programmable Gate Arrays) are useful compo-nents for embedded systems. In combination with Systems-on-Chip and Networks-on-Chip they enable flexible system solutions. Reliability and fault tolerance in such systems often is implemented by adding components for redundancy. Due to constraints in structural resources of FPGA chips, this approach in many cases does not provide adequate solutions. Indirect re-dundancy combined with universal component monitoring is a solution for failsafe Systems-on-Chip / Networks-on-Chip appli-cations in such situations.