Publikationen an der Fakultät für Informatik und Automatisierung ab 2015

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Irmak, Hasan; Corradi, Federico; Detterer, Paul; Alachiotis, Nikolaos; Ziener, Daniel
A dynamic reconfigurable architecture for hybrid spiking and convolutional FPGA-based neural network designs. - In: Journal of Low Power Electronics and Applications, ISSN 2079-9268, Bd. 11 (2021), 3, 32, insges. 25 S.

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.



https://doi.org/10.3390/jlpea11030032
Asghar, Ali; Hettwer, Benjamin; Karimov, Emil; Ziener, Daniel
Increasing side-channel resistance by netlist randomization and FPGA-based reconfiguration. - In: Applied reconfigurable computing, (2021), S. 173-187

Modern FPGAs are equipped with the possibility of Partial Reconfiguration (PR) which along with other benefits can be used to enhance the security of cryptographic implementations. This feature requires development of alternative designs to be exchanged during run-time. In this work, we propose dynamically alterable circuits by exploring netlist randomization which can be utilized with PR as a countermeasure against physical attacks, in particular side-channel attacks. The proposed approach involves modification of an AES implementation at the netlist level in order to create circuit variants which are functionally identical but structurally different. In preliminary experiments, power traces of these variants have been shuffled to replicate the effect of partial reconfiguration. With these dynamic circuits, our experimental results show an increase in the resistance against power side-channel attacks by a factor of [Tilde] 12.6 on a Xilinx ZYNQ UltraScale+ device.



Zhang, Yan; Müller, Steffen; Stephan, Benedict; Groß, Horst-Michael; Notni, Gunther
Point cloud hand-object segmentation using multimodal imaging with thermal and color data for safe robotic object handover. - In: Sensors, ISSN 1424-8220, Bd. 21 (2021), 16, 5676, insges. 16 S.

https://doi.org/10.3390/s21165676
Schatz, David; Roßberg, Michael; Schäfer, Günter
Hydra: practical metadata security for contact discovery, messaging, and dialing. - In: ICISSP 2021, (2021), S. 191-203

Communication metadata may leak sensitive information even when content is encrypted, e.g. when contacting medical services. Unfortunately, protecting metadata is challenging. Existing approaches for anonymous communications either are vulnerable in a strong (but feasible) threat model or have practicability issues like intense usage of asymmetric cryptography. We propose Hydra, a mix network that is able to provide multiple anonymous services in a uniform way. In contrast to previous messaging systems with strong anonymity, we deliberately use padded onion-encrypted circuits. This allows to support connectionless applications like contact discovery with authenticated key exchange, messaging, and dialing (signalling for connection-oriented communications) with strong anonymity and relatively low latency. Our cryptography benchmarks show that Hydra is able to process messages an order of magnitude faster than state of the art messaging systems with strong anonymity. At the same time, bandwidth overhead is comparable to previous systems. We further develop an analytical model to predict the end-to-end latency of Hydra and validate it in a testbed.



Schatz, David; Roßberg, Michael; Schäfer, Günter
Optimizing packet scheduling and path selection for anonymous voice calls. - In: ARES 2021, (2021), 12, insges. 10 S.

Onion routing is a promising approach to implement anonymous voice calls. Uniform-sized voice packets are routed via multiple relays and encrypted in layers to avoid a correlation of packet content in different parts in the network. By using pre-built circuits, onion encryption may use efficient symmetric ciphers. However, if packets are forwarded by relays as fast as possible - to minimize end-to-end latency - network flow watermarking may still de-anonymize users. A recently proposed countermeasure synchronizes the start time of many calls and batch processes voice packets with the same sequence number in relays. However, if only a single link with high latency is used, it will also negatively affect latency of all other calls. This article explores the limits of this approach by formulating a mixed integer linear program (MILP) that minimizes latency "bottlenecks" in path selection. Furthermore, we suggest a different scheduling strategy for voice packets, i.e. implementing independent de-jitter buffers for all flows. In this case, a MILP is used to minimize the average latency of selected paths. For comparison, we solve the MILPs using latency and bandwidth datasets obtained from the Tor network. Our results show that batch processing cannot reliably achieve acceptable end-to-end latency (below 400 ms) in such a scenario, where link latencies are too heterogeneous. In contrast, when using de-jitter buffers for packet scheduling, path selection benefits from low latency links without degrading anonymity. Consequently, acceptable end-to-end latency is possible for a large majority of calls.



https://doi.org/10.1145/3465481.3465768
Kuske, Dietrich;
Second-order finite automata: expressive power and simple proofs using automatic structures. - In: Developments in Language Theory, (2021), S. 242-254

Second-order finite automata, introduced recently by Andrade de Melo and de Oliveira Oliveira, represent classes of languages. Since their semantics is defined by a synchronized rational relation, they can be studied using the theory of automatic structures. We exploit this connection to uniformly reprove and strengthen known and new results regarding closure and decidability properties concerning these automata. We then proceed to characterize their expressive power in terms of automatic classes of languages studied by Jain, Luo, and Stephan.



Schlegel, Marius;
Poster: Shielding AppSPEAR - enhancing memory safety for trusted application-level security policy enforcement. - In: SACMAT '21, (2021), S. 99-101

This paper tackles the problem of memory-safe implementation of the AppSPEAR framework for application-level security policy enforcement. We contribute with a feasibility study that demonstrates the performance overhead of applying Rust's memory safety features on top of SGX trusted execution technology.



https://doi.org/10.1145/3450569.3464396
Lasch, Robert; Schulze, Robert; Legler, Thomas; Sattler, Kai-Uwe
Workload-driven placement of column-store data structures on DRAM and NVM. - In: DAMON '21: proceedings of the 17th International Workshop on Data Management on New Hardware (DaMoN 2021), (2021), 5, insges. 8 S.

Non-volatile memory (NVM) offers lower costs per capacity and higher total capacities than DRAM. However, NVM cannot simply be used as a drop-in replacement for DRAM in database management systems due to its different performance characteristics. We thus investigate the placement of column-store data structures in a hybrid hierarchy of DRAM and NVM, with the goal of placing as much data as possible in NVM without compromising performance. After analyzing how different memory access patterns affect query runtimes when columns are placed in NVM, we propose a heuristic that leverages lightweight access counters to suggest which structures should be placed in DRAM and which in NVM. Our evaluation using TPC-H shows that more than 80% of the data touched by queries can be placed in NVM with almost no slowdown, while naively placing all data in NVM would increase runtime by 53%.



https://doi.org/10.1145/3465998.3466008
Baumstark, Alexander; Jibril, Muhammad Attahir; Götze, Philipp; Sattler, Kai-Uwe
Instant graph query recovery on persistent memory. - In: DAMON '21: proceedings of the 17th International Workshop on Data Management on New Hardware (DaMoN 2021), (2021), 10, insges. 4 S.

Persistent memory (PMem) - also known as non-volatile memory (NVM) - offers new opportunities not only for the design of data structures and system architectures but also for failure recovery in databases. However, instant recovery can mean not only to bring the system up as fast as possible but also to continue long-running queries which have been interrupted by a system failure. In this work, we discuss how PMem can be utilized to implement query recovery for analytical graph queries. Furthermore, we investigate the trade-off between the overhead of managing the query state in PMem at query runtime as well as the recovery and restart costs.



https://doi.org/10.1145/3465998.3466011
Ortlepp, Ingo; Fröhlich, Thomas; Füßl, Roland; Reger, Johann; Schäffel, Christoph; Sinzinger, Stefan; Strehle, Steffen; Theska, René; Zentner, Lena; Zöllner, Jens-Peter; Rangelow, Ivo W.; Reinhardt, Carsten; Hausotte, Tino; Cao, Xinrui; Dannberg, Oliver; Fern, Florian; Fischer, David; Gorges, Stephan; Hofmann, Martin; Kirchner, Johannes; Meister, Andreas; Sasiuk, Taras; Schienbein, Ralf; Supreeti, Shraddha; Mohr-Weidenfeller, Laura; Weise, Christoph; Reuter, Christoph; Stauffenberg, Jaqueline; Manske, Eberhard
Tip- and laser-based 3D nanofabrication in extended macroscopic working areas. - In: Nanomanufacturing and metrology, ISSN 2520-8128, Bd. 4 (2021), 3, S. 132-148

The field of optical lithography is subject to intense research and has gained enormous improvement. However, the effort necessary for creating structures at the size of 20 nm and below is considerable using conventional technologies. This effort and the resulting financial requirements can only be tackled by few global companies and thus a paradigm change for the semiconductor industry is conceivable: custom design and solutions for specific applications will dominate future development (Fritze in: Panning EM, Liddle JA (eds) Novel patterning technologies. International society for optics and photonics. SPIE, Bellingham, 2021. https://doi.org/10.1117/12.2593229). For this reason, new aspects arise for future lithography, which is why enormous effort has been directed to the development of alternative fabrication technologies. Yet, the technologies emerging from this process, which are promising for coping with the current resolution and accuracy challenges, are only demonstrated as a proof-of-concept on a lab scale of several square micrometers. Such scale is not adequate for the requirements of modern lithography; therefore, there is the need for new and alternative cross-scale solutions to further advance the possibilities of unconventional nanotechnologies. Similar challenges arise because of the technical progress in various other fields, realizing new and unique functionalities based on nanoscale effects, e.g., in nanophotonics, quantum computing, energy harvesting, and life sciences. Experimental platforms for basic research in the field of scale-spanning nanomeasuring and nanofabrication are necessary for these tasks, which are available at the Technische Universität Ilmenau in the form of nanopositioning and nanomeasuring (NPM) machines. With this equipment, the limits of technical structurability are explored for high-performance tip-based and laser-based processes for enabling real 3D nanofabrication with the highest precision in an adequate working range of several thousand cubic millimeters.



https://doi.org/10.1007/s41871-021-00110-w