Hardware description languages: Verilog, VHDL

Responsible: Dr.-Ing. Steffen Arlt

target groups: 5th semester EIT, II, MT
 

Teaching content

  • Motivation/advantages of using hardware description languages
  • Classification in the design systematics of electronic systems
  • Learning the syntactic basic elements of VHDL and Verilog
  • Specific properties of VHDL and Verilog
  • Differences and similarities of the two hardware description languages
  • Simulation of designs
  • Synthesized modeling
  • Design examples
 

Internship
 

  • Implementation of a task in VHDL or Verilog
  • Simulation and synthesis of a system using Xilinx design tools
  • Implementation on an FPGA platform

 

Notes on teaching in the winter semester 2022/2023

 

The lectures and seminars take place in presence.

Detailed information can be found in Moodle, self-enrollment is also possible from 01.10.2022.