2D und 3D material morphologies

2D and 3D material morphologies for reactive micro joining in electronics

Contact person

Dr. Heike Bartsch
Department of Electronics Technology

Phone: +49 3677 69-3611
e-mail:  peter.schaaf@tu-ilmenau.de

Funding information

Project leader: Deutsche Forschungsgemeinschaft 

Project number: BA 6161/1-2

Participating groups: Department of Electronics Technology

Period of funding: 01.10.2023 - 30.09.2025


The project investigates the influence of the morphological characteristics and the physical properties of the joining partners on the microstructural characteristics of reactive multilayers on the thermophysical properties of the system and the reaction kinetics. The ultimate goal is a "suitable" microjoining process with suitable electrical and thermal properties for a high-quality mechanical joint. The focus is on the modification of the surfaces towards well-defined geometrically ordered and random morphologies. It is expected that the surface morphologies in combination with the physical properties of the substrate will influence the growth of the multilayers during sputtering and affect the microstructural properties of the Al/Ni RMS. The substrate properties can change the heat transfer conditions during self-propagation by influencing the rate and the maximum temperature. The cooling rate is also influenced, which affects the microstructure and morphology of the reaction products. Strategies for sequential and parallel ignition can be used to locally control heat distribution, preheating and cooling rates. Joining quality and defect analyses in the joining area are analyzed. Application rules for the selection of suitable surface structures and the RML design for high-quality joining processes are developed. These insights into the use of different architectures for chip joining will promote the development of prefabricated layer structures for future joining on the microscale in electronic packaging. The department of design rules for substrate morphology, 3D geometries and multilayer architecture with respect to reliable chip interconnects in electronic systems will enable customized packaging architecture for reactive electronic chip assembly in the future.