Cells

The Josephson Transmission Line (JTL) is the simplest cell of the RSFQ electronics. It is used for an active and quantum precise transmission of SFQ-pulses. Creating the JTL is the first step in a cell based design, where it is also important for minimizing the reciprocation between the other cells.

Those parameters belongs to a real layout, therefore the inductions don't have exactly the same value. The junctions has a McCumber-parameter of_βc=1 and a characteristic voltage of_IcRN= 250 μV. The agility of a junction is scaled by Sqrt(Jc). Thus the increase of the critical current density by factor 4 will decrease the time delay by factor 2. The advanced NEC process [2] for example provided a_Jc=10 kA, so the time delay is nearly 1,6 ps.

The current provided by the current supply_IB1 flows via_L2,_L3 and_J1,_J2 to ground. Both inductances have the same value, therefore the current is split up in two equal parts. The result is an equal phase drop across each junction in the initial state.

When an input SFQ pulse arrives it switches_J1 causing the phase at node 2 to rise by φ=2π. The result of this phase shift is an additional current flowing in the loop which is composed of_J1,_L2,_L3 and_J2. Combined with this current there is a magnetic flux quantum inside the loop. Whether this flux quantum is stored or not depends on the total inductance of the loop. In this particular case the total inductance is not large enough to hold the flux quantum, as a result the total current in_J2 is higher then the critical current. The junction switches and the SFQ pulse leaves the cell by the output. After this brief event the cell is again in the initial state.

The time delay per junction depends on the critical current density. The maximum critical current density provided by the JeSEF process is J=1 kA, thus the time delay is about 5ps per junction. The time delay caused by the whole JTL is about 10,5 ps.

The first step of designing a new cell library is creating the JTL. Usually identical parameters are used for all elements inside a JTL. That means there are only three degrees of freedom, which are the critical current and the bias current of a junction as well as the inductances. To achieve the best stable cell and to minimize the influence of noise, the critical current of the junction has to be as high as possible. But there is an upper bound given by the technology parameters, which is described by the maximum critical current of the technology_Ic,MAX. It is wise to use a critical current for the JTL, which is lower than_Ic,MAX, because there are many different circuit structures, for which the possibility to build bigger junctions as this one of the JTL is needed. It is usual to take a Sqrt(2) times smaller value as the maximum possible critical current [3]. This means:

For the bias current of a junction it is common to take a value between 0,6 and 0,75 times of the critical current. The higher the value the faster the junction can switch. But a lower bias current provides a more stable cell. It was decided to use a bias current of:

The last parameter to be discussed is the inductance. The optimal inductance of a JTL can be calculated by [4]:

while_Ic is the critical current of the JTL junctions and_IB is the bias current. The result is the inductance of the whole loop. It is composed by the inductances_L2,_L3 and the parasitic inductances_Lp1,_Lp2. This means:

1. P. Bunyk, K. Likharev and D. Zinoview RSFQ technology: physics and devices. Int. Journal on High Speed Electronics and Systems, vol. 11, No. 1, pp. 257-306, 2001. doi.org/10.1142/S012915640100085X
2. H. Akaike, T. Yamada, A. Fujimaki, S. Nagasawa, K. Hinode, T. Satoh, Y. Kitagawa and M. Hidaka Demonstration of 120 GHz Single Flux Quantum Circuits Based on a 10 kA/cm² Nb Process. Extended Abstracts of 10th ISEC, Noordwijkerhout, 5.-9.9.2005.
3. P. Bunyk, K. Likharev, P. Litskevitch, A. Rylyakov and D. Zinoview RSFQ cell library. Technical Report 15, SUNY at Stony Brook, May 1999. http://pavel.physics.sunysb.edu/RSFQ/publications.html
4. Th. Ortlepp Dynamische Analyse stochastischer Einflüsse in der supraleitenden Einzelflussquantenelektronik. Ph.D. thesis, Technical University Ilmenau, 2004.

The Splitter doubles the SFQ pulses. When there is an input SFQ pulse the splitter produced two output pulses at two different output ports. The splitter is a non-storing cell like the JTL. Therefore it is also possible to create the cell without using an optimization tool.

To achieve a stable functionality of the cell the output ports have to be symmetrical. The Splitter is composed by three JJs. All of them are biased by one current supply. If a SFQ pulse arrives at the input,_J1 is switching. The result is a 2π phase leap across the junction, increasing the current in both branches_L4-J2 and_L6-J3. The resulting current exceeds the critical current in both junctions. Both junctions switch simultaneously and a SFQ pulse leaves the cell by each output.

The delay of this Splitter is about 12,8 ps. Thus the delay is nearly 20% higher than the one of the JTL. The reason for the time difference is the decision the junctions have to do. There are two ways for the cell to achieve a stable state. The first possibility was already mentioned,_J2 and_J3 have to switch. The second alternative is_J1 switch back, but this has to be avoided for a correct functionality. That's why_J1 is stronger than the others.

One can also recognize the decision-making process in the diagram of the transient simulation. The short intermezzo in the phase rise is caused by that process.

The Splitter is a non storing circuit, that's why it is possible to achieve that no current is flowing through the I/O port in the static state. That's for the phase shift across the junctions of the Splitter have to be the same as this one of the junctions of the neighbor JTL. The phase shift depends on the ration between the bias current and the critical current of a junction. During the design of the JTL it was decided to use a ratio of:

The first step is to calculate the current, provided by the current supply_IB1. The total current is composed by the bias current of_J1,_J2 and_J3. The critical current of_J2 has to be the same as the one of_J3 because of the forced symmetry of the output. This means that:

The whole bias current can be written as:

The next step is to calculate the inductances, so that the current of_IB1 will be splitting up in the right ratio. There for it is necessary to evaluate the substitute inductance of the virtual loop which contains_L2,_L3,_L4 and_L6. The total inductance can be expressed by:

To achieve a more accurate solution this formula can be completed by the additional inductance generate by the junctions and the parasitic inductance of each branch. For example_L4 in this formula can be written as

The value for the inductance of the junction can be calculated by:

To reach the symmetry of the output ports the inductance of both branch has to be identical, that's way a new variable can be establish:

With these equations it is possible to calculate the unknown inductances by using the theorem of Kirchhoff:

To figure those equations out one need a value for_Lsub. There for the Splitter is to treat as a non-storing loop. It is wise to choose the inductance for that kind of loop as:

In this special case the current is composed by:

To satisfy those equations the inductance_L3 is zero. Thus this inductance isn't necessary for the theoretical design, but it is required for the layout of this cell.

1. P. Bunyk, K. Likharev and D. Zinoview RSFQ technology: physics and devices. Int. Journal on High Speed Electronics and Systems, vol. 11, No.1, pp. 257-306, 2001.doi.org/10.1142/S012915640100085X
2. J. Weber, Th. Ortlepp Investigation of the switching and delay times of a superconducting high-speed electronics in the picosecond range. master thesis, TU Ilmenau, 2003.

This cell is used as an interface between the superconductive electronics and a superconductive passive transmission line (PTL). Therefore it is essential that the input match to a standard JTL and the output should have the impedance of the transmission line.

In different to the standard properties the junction_J2 was designed with a McCumber parameter_βc=4.

For transmitting SFQ pulses the JTL was introduced, but this cell has some disadvantages. For example the great number of junctions which are required to overcome long distances. That's caused a great time delay and a great power consumption. Furthermore such a way of connecting required a lot of space. All this things can be avoid by using a PTL, usually is a microstrip transmission line (MSL). Only the voltage pulse is transmitted by such a structure. Thus PTL's provide transmissions with the speed of light dependent of a certain substrate. Since PTL's do not use JJ's the power consumption is independent of the length.

The PTL Driver has to decouple the voltage pulse and the magnetic flux. That's way the resistor is so important to disrupt the superconductivity and to spread the magnetic flux. The consequence of which is the transmission isn't quantum precise.

Furthermore this resistor is necessary to establish a impedance matching between the SFQ electronics and the microstripline to avoid reflection. Such reflections cannot completely eliminate, but they have to be minimized to ensure that the reflected wave is not strong enough to switch the JJ. Beyond it is possible that reflected waves are accumulated in the PTL and affect the driver and receiver operation. The resonance phenomenon is a particular problem in PTL's but does not exist in conventional JTL interconnections [2].

1. N. Joukov, Y. Hashimoto and V.K. Semenov Matching Josephson Junctions with Microstrip Lines for SFQ Pulses and Weak Signals. IEICE Transaction on Electronics, vol. E85-C, No.3, pp. 636-640, 2002.
2. Y. Hashimoto, S. Yorozu, A. Fujimaki, H. Terai and N. Yoshikawa Development of Passive Intercinnection Technology for SFQ Circuits. IEICE Transaction on Electronics, vol. E88, No.2, pp. 198-207, 2005.
3. J. Pleikies, Th. Ortlepp Entwurf eines Datenschalters für ultraschnelle Kommunikationsnetze unter Anwendung der Einzelflussquantenelektronik. master thesis, TU Ilmenau, 2005.

The receiver is the counter part to the PTL-Driver. It is also in interface between a passive transmission line and the RSFQ electronics. In the process the input signal is a voltage peak and the output signal is a SFQ pulse.

In different to the standard properties the junction_J1 was designed with a McCumber parameter_βc=4.

The input signal is a voltage pulse coming from the passive transmission line. This pulse has to be strong enough to initiate a switching operation of the junction_J1. The pulses transmitted by a JTL are automatically refreshed, that is the main difference to a transmission by a PTL's. Voltage signals carried by a microstripline are damped and distorted because of a frequency dependent velocity of propagation. For short PTL's the influence of both effects is negligible but as longer the distance as higher is the probability of a data loss. In that case a incoming voltage pulse is to weak for initiating a switching operation.

Moreover the energy loss in a PTL is almost negligible for on-chip distances from this point of view lengths of 4 mm are uncritical and already realized [1]. Much more problems are induced by the resonance phenomenon.

The receiver consists of two junctions. The first junction,_J1, acts as a receiver, after the switching of this component the information is coupled to a SFQ pulse again. The second stage of this cell has the same parameters as one half of our standard JTL. Thus, the matching condition between the PTL and the receiver is unaffected from the follows circuit.

A time delay of nearly 6 ps caused by the microstripline is the conclusion of the transient simulation. This is approximately the same delay like this one of the JTL but the distances are completely different. While the JTL is 150 μm long the microstripline is 700 μm long. Thus the signal takes 8.6 ps/mm [2] in a PTL this corresponds to the experimental extracted value presented in [3].

1. Y. Hashimoto, S. Yorozu, A. Fujimaki, H. Terai and N. Yoshikawa Development of Passive Intercinnection Technology for SFQ Circuits. IEICE Transaction on Electronics, vol. E88, No.2, pp. 198-207, 2005.
2. J. Pleikies and Th. Ortlepp Entwurf eines Datenschalters für ultraschnelle Kommunikationsnetze unter Anwendung der Einzelflussquantenelektronik. master thesis, TU Ilmenau, 2005.
3. Y. Hashimoto, S. Yorozu, Y. Kameda, and V.K. Semenov A Design Approach to Passive Interconnects for Single Flux Quantum Logic Circuits. IEEE Transactions on Applied Superconductivity, vol. 13, No.2, pp. 535-538, June 2003. doi.org/10.1109/TASC.2003.813929

The Delay Flip-Flop (DFF) is a bistable clocked basic cell with the ability of data storing. While data input and storing is an asynchron process, data output is triggered by a clock signal. A SFQ pulse entering the DFF device through the data input port is stored inside the cell until a clock signal appears. If that the case a SFQ pulse is leaving the cell trough the output port. In doing so the inner state of the device is switching back to the initial state. So the output signal is only generated if an input signal reached the cell between two clock pulses and if a clock pulse triggered it.

The DFF is a basic cell of particular importance for RSFQ electronics. Because of the pulse driven nature of RSFQ almost all logic cells need the abilities of temporary data latching. Due to most of the standard logic devices have DFF likewise structures. Usually this cell is also used as a component of a shift register.

In principle there are two kinds of Toggle Flip-Flop (TFF) in RSFQ electronics. Basically both have the similar behavior. Each of them has tow stable states and toggles between them whenever an input pulse is entering the cell through its single input port. The TFFs differ in the number of output ports.

The version with two outlets is transferring each time the incoming pulse, but through alternating ports depending on the state of the cell. This device works like a demultiplexer, splitting up a data stream to two signal lines.

The type with a single output port is generating an output pulse at every other input signal. This cell acts as a frequency divider, at which the output frequency is a half of the input frequency. In the following the function of this device will be analyzed.

As mentioned before, a TFF has two stable states "1" and "0" characterized by the number of flux quanta stored in the storage loop_{L34-J4-L8-L7-L6-J5-L5}.

In the initial state "0" no flux quantum is stored in the loop. An incoming SFQ pulse entering the cell through_J7 and_J1 causes an additional current. This splits up at node 3 and flows through_J2 and_J3 to ground. The switching of the junctions_J2 and_J5 is favored by the bias current. Because of there switching a flux quantum is entering the storage loop and causes an additional current, which is superposing the bias current. The device is now in state "1", in which the current distribution favors now the switching of_J3 and_J4, so they will switch if a second pulse arrives. In doing so the flux quantum is leaving the storage loop and the device is again in the initial state "0", after a second SFQ pulse was arriving the cell.

Since there is a close coupling between_J3 and the output junction_J6, caused by the small inductance_L6, they switch together. That means, a SFQ pulse will leave the device through the output port, if it toggles from state "1" to "0".

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