Neuromorphic Memristive VLSI Architectures for Cognition

Contact person

Prof. Martin Ziegler
Micro- an Nanoelectronic Systems Group

Phone: +49 3677 69-3711
e-mail: martin.ziegler@tu-ilmenau.de

Funding information

Project leader: Deutsche Forschungsgemeinschaft 

Project number: ZI 1548/6-1

Participating groups: Micro- and Nanoelectronic Systems Group

Period of funding: 01.04.2020 - 30.05.2024


The implementation of biologically inspired "spiking neutral networks" (SNN) is strongly affected by the exponentially increasing discrepancy between processor speed and memory bandwidth, which is characteristic of Neumann computer architectures. Therefore, the simulation of processing elements of neural networks (neurons and synapses) requires a high memory utilization during access and updating of their state variables. This so-called "von Neumann bottleneck" limits the real-time replication of large networks and makes their modular expandability difficult. In contrast, highly parallel and energy-efficient neuromorphic analog (VLSI) systems can be extended by colocalization of memory and computation without affecting the simulation time. The goal of this project is the development of fully integrated CMOS/memrisitive systems, which are optimized for the simulation of learning neural networks. For the implementation of biologically-inspired learning algorithms, the stochastic switching behavior of binary PRAM devices shall be used. The devices will be integrated into state-of-the-art analog CMOS circuits operating below the threshold voltage. This combination shall lead to the creation of learning systems with unprecedented low power consumption, which also work in real-time and allow online learning. For this purpose, the memristive components will first be characterized in detail within the project. The memristive components will be HfOx based COMOS integrated PRAM cells, which have a binary switching characteristic. The goal is to develop a mathematical model of the stochastic switching behavior which can be used for the realization of precise SPICE simulations of hybrid CMOS/memristor circuits as well as for the simulation of realistic SNNs and which supports the hardware circuit design.