Congress contributions

To keep up with Moore's law in future, the critical dimensions of device features must further decrease in size. Thus, the nano-electronics and nano-optics manufacturing is based on the ongoing development of the lithography and encompasses also some unconventional methods. In this context, we use the Nanopositioning and Nanomeasuring Machine (NPMM) to generate features in resist layers by means of Direct Laser Writing (DLW),1 Field Emission Scanning Probe Lithography (FE-SPL)2 and Soft UV-Nanoimprint Lithography (Soft UV-NIL)3 with highest accuracy. The NPMM was collaboratively developed by TU Ilmenau and SIOS Meßtechnik GmbH.4 The tool provides a large positioning volume of 25 mm × 25 mm × 5 mm with a positioning resolution of 0.1 nm and a repeatability of less than 0.3 nm over the full range. Previously a single electron transistor (SET) working at room temperature generated by FE-SPL has been demonstrated.5 However, the throughput is limited because of the serial writing scheme making Tennant's law (At R5 ) valid.6 Here, At is the areal throughput and R the lithographic resolution. Thus, patterning of the whole NPMM positioning area by FE-SPL is very time consuming. In order to address this problem, different strategies and/or combinations are conceivable. In this work a so-called Mix-and-Match lithography is conducted. A fast generation of structures in the sub-micron range is possible by means of DLW. By this, features such as electrical wires, contact patches for bonding or labels are generated in resist. Subsequently, we use FE-SPL in order to define the actual nano-scaled features for quantum or single electron devices. In combination, DLW and FE-SPL are maskless lithography strategies, hence, offering completely novel opportunities for rapid nanoscale prototyping of largescale resist patterns. An explanation of this technique is given in a previous publication.7 Furthermore, after reactive ion etching, the sample can be used as template for Soft UV-NIL, thus resulting in a high-throughput process chain for future quantum and/or single electron devices.