Technische Universität Ilmenau Department of Computer Science and Automation Institute of Computer and Systems Engineering Group for Computer Architecture and Embedded Systems
Helmholtzplatz 5 98693 Ilmenau Zusebau, room Z 2056
The research area Computer Architecture and Embedded Systems is very versatile. Due to the increasing interconnection of electronic systems and the advances in semiconductor technology, which allows to design more and more complex systems, the importance of this research area has increased significantly in the last years. Due to mobile, battery-powered systems on the one hand and the processing of enormous amounts of data (keyword: Big Data) in huge data centers on the other hand, the energy efficiency of computer systems is becoming increasingly important. However, the increasing miniaturization and complexity also brings problems. For example, transistors are becoming increasingly unreliable, and hardware attacks on computing systems are on the rise. We are, therefore, investigating adaptive systems,whichcan adapt to new requirements and threats. However, new architectural concepts, such as many cores with thousands of processor cores, network-on-chips, or new technologies, such as memristors, are also being considered.
The focus of research is on so-called reconfigurable hardware systems which implement a circuit structure with the help of a configuration . The research area of architectures of such reconfigurable hardware systems as well as algorithms and applications with reconfigurable hardware systems is also called Reconfigurable Computing
Free Pixabay License (id-6382593)
The mainly used reconfigurable devices are the so-called Field Programmable Gate Arrays (FPGAs) which belong to the family of PLDs (Programmable Logic Devices). FPGAs are digital chips that can be programmed for implementing arbitrary digital circuits. This means that FPGAs must first be programmed with a so-called configuration (often referred to as a configuration bitstream) to set the desired behaviour of the functional elements of the FPGA. FPGAs have a significant market segment in microelectronics and especially in the field of embedded systems.
Dynamic reconfiguration of FPGAs means the exchange of the FPGA configuration during runtime. Partial dynamic reconfiguration means that only certain parts of the configuration are exchanged at runtime, whereas the rest of the configuration remains active. Dynamic and especially partial reconfigurations require additional hardware support from the FPGA's configuration manager.
FPGAs have physically supported partial reconfiguration for several years. However, its use for industrial designs is still in its infancy and does not yet exploit the great possibilities that partial dynamic reconfiguration could offer.
In addition to the technical support provided by the FPGA, partial reconfiguration also requires a suitable design process to build such a system. A partially reconfigurable design is usually divided into two parts: The
a) static part is always present and is only configured when the system is switched on. This part usually contains the interfaces to peripheral devices, memory controllers, and access to the configuration interface of the FPGA (e.g., the ICAP for Xilinx FPGAs). The configuration of one or more
b) partially reconfigurable parts or areas can be exchanged at runtime. These areas are usually embedded and surrounded by the static part. In these partially reconfigurable areas, modules and operations are implemented that can be adapted or exchanged at runtime.
By using partial dynamic reconfiguration, flexible adaptive digital circuits can be realised. These adaptive digital circuits are able to modify their structure at runtime to cope with environmental or requirement changes, including different user requirements. By using this technique, a high degree of flexibility can be achieved, which, properly used, leads to energy-efficient and high-performance implementations. On the other hand, such circuits are able to withstand harsh environmental conditions by responding quickly to environmental changes through structural adaptation. This behaviour leads to a more reliable system if, for example, the reconfigurable system can adapt to certain radiation levels. Furthermore, the security of an FPGA-based implementation against physical attacks such as side-channel analysis, fault injection attacks or reverse engineering can be increased enormously.
In the following, the main research topics of the group "Computer Architecture and Embedded Systems" will be discussed:
Composed from Free Pixabay license
Today's modern FPGA architectures consist of hundreds of thousands of lookup tables and flip-flops that can accommodate enormously powerful and complex system-on-chips (SoCs). In addition, these architectures can be reconfigured in a very fine-granular way. However, the development tools of FPGA manufacturers by far do not exploit this adaptivity. Furthermore, these development tools are usually trimmed to the performance of the resulting circuit and usually disregard other non-functional properties such as reliability or protection against attacks.
Through extensions of the design flow, also on lower levels, very fine-granular partially dynamically reconfigurable systems can be designed on the one hand, but also non-functional properties of the systems can be improved. By integrating high-level synthesis tools, the abstraction level for the developer can be raised and design productivity increased. On the other hand, new FPGA architectures can be developed and investigated that support, for example, very fast reconfiguration.
Free Pixabay license (id-1616966)
The particular importance of energy efficiency for battery-powered systems is obvious. However, energy efficiency is also crucial for the sustainable and economic operation of large data centres and communication networks. The amount of data created, captured, or processed each year increases by a factor of 10 every five years. Storing all this data is one challenge - processing and analysing it is another. In fact, the enormous increase in the amount of data even surpasses Moore's Law. This means that we cannot process the ever-growing amount of data with more processing resources alone. The energy consumption of all data centres worldwide is increasing by 16.7% annually. In 2013, the energy consumption of all IT facilities together accounted for 10% of global energy production and will continue to rise. New energy-efficient systems are needed here, which will be developed and investigated in this research focus.
Free Pixabay license (id-505878)
Due to increasing intra- and inter-die process variability (Leff, Weff, doping , Vth), heat radiation above 100 W/cm2, as well as increasing sensitivity to radiation, transistors in future CMOS process generations will become increasingly unreliable. The challenge of building reliable systems from potentially unreliable devices will be addressed in this research area. In the area of reliability of digital systems, dynamic countermeasures to radiation-induced or age-related errors are investigated. One example is a fault-tolerant adaptive satellite system that can adapt to changes in radiation dose by reconfiguration. Furthermore, ageing effects of FPGAs and integrated circuits are investigated.
Free Pixabay License (id-4993196)
Physical attacks such as side-channel analysis, fault injection attacks, or classic reverse engineering pose a massive threat to any cryptographic implementation. For cryptographic hardware implementations that are exposed to such physical attacks, it is essential to take efficient countermeasures. FPGAs are an efficient platform for cryptographic hardware implementations. However, to be protected against physical attacks, any security-critical circuit implemented on an FPGA must be protected against the above threats. Techniques are being developed that utilise the dynamic reconfiguration of FPGAs as effective protection mechanisms against the above classes of attacks.
Composed from Free Pixabay license
Today, modern computers and embedded systems are being asked to perform increasingly computationally intensive tasks. While some tasks should be processed as quickly as possible (e.g., searching a data set in a database), others have an upper limit for the execution time (e.g., collision detection in robotics - see real-time systems). One way to meet these requirements is to use special optimised hatdware circuits for specific problems, called accelerators. Prominent examples of accelerators can be found, for example, in image processing, cryptography, and artificial intelligence. FPGAs, with their ability to implement arbitrary digital circuits, are particularly suitable for prototyping and evaluating individual accelerators and accelerator-based systems. Adaptive accelerators can be realised with the help of dynamic partial reconfiguration. Such accelerators can be used, for example, in data centres where FPGAs dynamically perform a wide variety of tasks. The major challenges of data acceleration in data centres with different complex requests and load scenarios is the early efficient filtering of huge amounts of data, as well as the virtualisation of the acceleration hardware to guarantee low response times for a large number of users. In addition to the architectures of accelerators, concepts for the efficient embedding of accelerators are also being investigated. Approaches that embed accelerators directly in the data streams, such as in the memory or network controllers, will be investigated.
Free Pixabay license (id-564784)
With programmable hardware, especially FPGAs, so-called "softcore processors" can be implemented. These can be adapted to the concrete application in many ways. This makes more efficient solutions possible that have advantages over fixed processors in terms of functionality, energy consumption, structural effort, or programming effort. For the design of such processors, special design flows are needed that guide the designer to an optimal solution based on a model. In this research area, the architectures of softcore processors and suitable design procedures are investigated.
