Prof. Dr.-Ing. habil. Daniel Ziener

Head of group RAES

Group for Computer Architecture and Embedded Systems
Department of Computer Science and Automation
Technische Universität Ilmenau
Helmholtzplatz 5 (Zusebau)

98693 Ilmenau, Germany
 

✉ daniel.ziener@tu-ilmenau.de
☎ +49 3677 69-2825 (secretary)
☎ +49 3677 69-2827
🏘 Z 2056

About Me

Daniel is currently a Full Professor for Computer Architecture and Embedded Systems at the faculty Computer Science and Automation of the Technische Universität Ilmenau, Germany. From 2018 to 2021, he was an Associate Professor in the CAES group (Computer Architecture for Embedded Systems) at the University of Twente, the Netherlands. From 2015 until 2017, he was a substitute professor for Cyber-Physical Systems at the Hamburg University of Technology, Germany. Furthermore from 2010 to 2015, he had led the Reconfigurable Computing Group of the Chair of Hardware/Software Co-Design at Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany.

His main research interests are the usage of partial dynamic reconfiguration of FPGAs, efficient usage of FPGA structures, design of signal processing FPGA cores, reliable and fault tolerant embedded systems, as well as security in FPGA-based systems. Daniel has (co-)authored more than 40 peer-reviewed publications, holds three patents, and serves as a program committee member of several international conferences (DATE, FPL, Reconfig, SPL) as well as a reviewer for several international journals.

Daniel took his university entrance qualification in 1998. He received his diploma degree (Dipl.-Ing. (FH)) in Electrical Engineering from University of Applied Science Aschaffenburg, Germany, in August 2002. Beside his studies, he gained industrial research experience during an internship at the IBM Germany Development Labs in Böblingen. From 2003 to 2009 he worked for the Fraunhofer Institute of Integrated Circuits (IIS) in Erlangen, Germany as a research staff in the electronic imaging department. Furthermore, in 2003 he joined the Chair of Hardware-Software-Co-Design at the University of Erlangen-Nuremberg, Germany, headed by Prof. Jürgen Teich as PhD student. In 2010 he received his PhD degree (Dr.-Ing.) and in 2017 his habilitation (Dr.-Ing. habil.).

Research Interests

  • Partial dynamic reconfiguration of FPGAs
  • Efficient usage of FPGA structures
  • Design of signal processing FPGA cores
  • Reliable and fault tolerant embedded systems
  • Secure embedded systems
  • IP core watermarking

Publications

Google Scholar

2022

  • Ali Asghar, Andreas Becher, and Daniel Ziener
    "The benefits and costs of netlist randomization based side-channel countermeasures: An in-depth evaluation"
    Journal of Low Power Electronics and Applications, July 2022, [DOI]

2021

  • Hasan Irmak, Federico Corradi, Paul Detterer, Nikolaos Alachiotis, and Daniel Ziener
    "A dynamic reconfigurable architecture for hybrid spiking and convolutional fpga-based neural network designs"
    Journal of Low Power Electronics and Applications, August 2021, [DOI]
  • Hasan Irmak, Daniel Ziener, and Nikolaos Alachiotis
    "Increasing flexibility of fpga-based CNN accelerators with dynamic partial reconfiguration"
    In 31st International Conference on Field-Programmable Logic and Applications, FPL 2021, Dresden, Germany, August 30 - Sept. 3, 2021, August 2021, [DOI]
  • Ali Asghar, Benjamin Hettwer, Emil Karimov, and Daniel Ziener
    "Increasing side-channel resistance by netlist randomization and fpga-based reconfiguration"
    In Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings, June 2021, [DOI]
  • Hasan Irmak, Nikolaos Alachiotis, and Daniel Ziener
    "An energy-efficient fpga-based convolutional neural network implementation"
    In 29th Signal Processing and Communications Applications Conference, SIU 2021, Istanbul, Turkey, June 9-11, 2021, June 2021, [DOI]

2020

  • Pepijn de Vos, Michael Kirchhoff, and Daniel Ziener
    "A complete open source design flow for gowin fpgas"
    In International Conference on Field-Programmable Technology, (IC)FPT 2020, Maui, HI, USA, December 9-11, 2020, December 2020, [DOI]

2019

  • Ali Asghar, Rick van Loo, Timon Kruiper, and Daniel Ziener
    "Optimizing FPGA-based Streaming Applications for Throughput Using Pipelining"
    In Proceedings of the International Conference on Field Programmable Technology (FPT 2019), December 2019, [DOI]
  • Daniel Ziener
    "Security in embedded hardware"
    Universiteit Twente, December 2019
  • Michaela Blott, Ling Liu, Daniel Ziener, and Kimon Karras
    "Pipelined database processing circuit and method" (10482129)
    19 November 2019

2018

  • Daniel Ziener, Jutta Pirkl, and Jürgen Teich
    "Configuration tampering of BRAM-based AES implementations on FPGAs"
    In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig 2018), December 2018, [DOI]
  • Thorbjörn Posewsky and Daniel Ziener
    "Throughput optimizations for FPGA-based deep neural network inference"
    Microprocessors and Microsystems, 151 — 161, July 2018, [DOI]
  • Thorbjörn Posewsky and Daniel Ziener
    "A Flexible FPGA-based Inference Architecture for Pruned Deep Neural Networks"
    In Proceedings of the International Symposium on Applied Reconfigurable Computing (ARCS 2018), May 2018, [DOI]

2017

  • Daniel Ziener
    "Improving Reliability, Security, and Efficiency of Reconfigurable Hardware Systems (Habilitation)"
    December 2017
  • Bernhard Schmidt, Daniel Ziener, Jürgen Teich, and Christian Zöllner
    "Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning"
    Integration, the VLSI Journal, 98 — 108, September 2017, [DOI]

2016

  • Thorbjörn Posewsky and Daniel Ziener
    "Efficient Deep Neural Network Acceleration through FPGA-based Batch Processing"
    In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig 2016), December 2016, [DOI]
  • Jorge Alfonso Echavarria Gutiérrez, Stefan Wildermann, Andreas Becher, Jürgen Teich, and Daniel Ziener
    "FAU: Fast and error-optimized approximate adder units on LUT-based FPGAs"
    In Proceedings of 2016 International Conference on Field Programmable Technology (FPT), 7 - 9 December 2016, Xi'an, China, [DOI]
  • Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, and Helmut Weber
    "FPGA-Based Dynamically Reconfigurable SQL Query Processing"
    ACM Transactions on Reconfigurable Technology and Systems (TRETS), 1 — 25, August 2016, [DOI]
  • Andreas Becher, Jorge Alfonso Echavarria Gutiérrez, Daniel Ziener, Stefan Wildermann, and Jürgen Teich
    "A LUT-based approximate adder"
    In 24th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), 1 - 3 May 2016, Washington, DC, USA, [DOI]
  • Dirk Koch, Frank Hannig, and Daniel Ziener
    "Fpgas for software programmers"
    Springer, January 2016, [DOI]
  • Dirk Koch, Daniel Ziener, and Frank Hannig
    "FPGA versus software programming – why, when, and how?"
    In FPGAs for Software Programmers, ch. 1
    Edited by Dirk Koch, Frank Hannig, and Daniel Ziener
    January 2016, [DOI]

2015

  • Andreas Becher, Daniel Ziener, Klaus Meyer-Wegener, and Jürgen Teich
    "A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering"
    In 2015 International Conference on Field Programmable Technology (FPT), 7 - 9 December 2015, Queenstown, New Zealand, [DOI]
  • Jorge Alfonso Echavarria Gutiérrez, Andreas Becher, Jürgen Teich, and Daniel Ziener
    "Approximate Adder Structures on FPGAs"
    In AxC15: 1st Workshop on Approximate Computing, 15 - 16 October 2015, Paderborn, Germany
  • Frank Hannig, Dirk Koch, and Daniel Ziener
    "Proceedings of the second international workshop on fpgas for software programmers (fsp 2015)"
    London, United Kingdom, 1 September 2015, [DOI]
  • Robert Glein, Florian Rittner, Andreas Becher, Daniel Ziener, Jürgen Frickel, Jürgen Teich, and Albert Heuberger
    "Reliability of space-grade vs. COTS SRAM-based FPGA in n-modular redundancy"
    In Proceedings of 2015 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 15 - 18 June 2015, Montreal, QC, Canada, [DOI]

2014

  • Andreas Becher, Florian Bauer, Daniel Ziener, and Jürgen Teich
    "Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration"
    In Proceedings of the Conference on Field-Programmable Logic and Applications (FPL), 2 - 4 September 2014, Munich, [DOI]
  • Frank Hannig, Dirk Koch, and Daniel Ziener
    "Proceedings of the first international workshop on fpgas for software programmers (fsp 2014)"
    Munich, Germany, 1 September 2014, [DOI]
  • Bernhard Schmidt, Daniel Ziener, and Jürgen Teich
    "Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning"
    In Proceedings of the Reconfigurable Architectures Workshop (RAW), May 2014, [DOI]
  • Robert Glein, Bernhard Schmidt, Florian Ritter, Jürgen Teich, and Daniel Ziener
    "A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor"
    In Proceedings of Field-Programmable Custom Computing Machines (FCCM 2014), May 2014, [DOI]
  • Bernhard Schmidt, Daniel Ziener, and Jürgen Teich
    "An Automatic Netlist and Floorplanning Approach to Improve the MTTR of Scrubbing Techniques (Abstract Only)"
    In Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays, May 2014, [DOI]
  • Bernhard Schmidt, Daniel Ziener, and Jürgen Teich
    "A Netlist Analysis Approach to Classify FPGA Configuration Bits in order to Optimize Scrubbing"
    In Proceedings of the 8th HiPEAC Workshop on Reconfigurable Computing (WRC), 21 January 2014

2013

  • Stefan Wildermann, Felix Reimann, Daniel Ziener, and Jürgen Teich
    "Symbolic System-level Design Methodology for Multi-Mode Reconfigurable Systems"
    Journal on Design Automation for Embedded Systems, 343 — 375, June 2013, [DOI]
  • Christopher Dennl, Daniel Ziener, and Jürgen Teich
    "Acceleration of SQL Restrictions and Aggregations through FPGA-based Dynamic Partial Reconfiguration"
    In Proceedings of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), April 2013, [DOI]

2012

  • Tobias Ziermann, Alexander Butiu, Daniel Ziener, and Jürgen Teich
    "FPGA-based Testbed for Timing Behavior Evaluation of the Controller Area Network (CAN) "
    In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), December 2012, [DOI]
  • Stefan Wildermann, Felix Reimann, Daniel Ziener, and Jürgen Teich
    "System Level Synthesis Flow for Self-adaptive Multi-mode Reconfigurable Systems"
    In Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS 2012), 1 September 2012
  • Christopher Dennl, Daniel Ziener, and Jürgen Teich
    "On-the-fly Composition of FPGA-Based SQL Query Accelerators Using A Partially Reconfigurable Module Library"
    In Proceedings of the IEEE International Field-Programmable Custom Computing Machines Symposium (FCCM), May 2012, [DOI]
  • Dirk Koch, Jim Torresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, and Walter Stechele
    "Partial Reconfiguration on FPGAs in Practice - Tools and Applications"
    In Proceedings of the 2012 Architecture of Computing Systems (ARCS'12), February 2012

2011

  • Tobias Ziermann, Bernhard Schmidt, Moritz Mühlenthaler, Daniel Ziener, Josef Angermeier, and Jürgen Teich
    "An FPGA Implementation of a Threat-based Strategy for Connect6"
    In Proceedings of the International Conference on Field-Programmable Technology (FPT), December 2011, [DOI]
  • Josef Angermeier, Daniel Ziener, Michael Glaß, and Jürgen Teich
    "Runtime stress-aware replica placement on reconfigurable devices under safety constraints"
    In Proceedings of the International Conference on Field-Programmable Technology (FPT), December 2011, [DOI]
  • Stefan Wildermann, Felix Reimann, Daniel Ziener, and Jürgen Teich
    "Symbolic Design Space Exploration for Multi-mode Reconfigurable systems"
    In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2011, [DOI]
  • Josef Angermeier, Daniel Ziener, Michael Glaß, and Jürgen Teich
    "Stress-Aware Module Placement on Reconfigurable Devices"
    In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), August 2011, [DOI]
  • Stefan Wildermann, Jürgen Teich, and Daniel Ziener
    "Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs"
    In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), August 2011, [DOI]
  • Daniel Ziener, Stefan Wildermann, Andreas Oetken, Andreas Weichslgartner, and Jürgen Teich
    "A Flexible Smart Camera System based on a Partially Reconfigurable Dynamic FPGA-SoC"
    In Proceedings of the Workshop on Computer Vision on Low-Power Reconfigurable Architectures at the FPL 2011, August 2011
  • Jürgen Teich and Daniel Ziener
    "Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques"
    In Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'11), July 2011

2010

  • Daniel Ziener and Jürgen Teich
    "New Directions for FPGA IP Core Watermarking and Identification"
    In Dagstuhl Seminar 10281 Proceedings, December 2010
  • Daniel Ziener, Moritz Schmid, and Jürgen Teich
    "Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores"
    In Design Methodologies for Secure Embedded Systems, ch. 6
    Edited by A. Biedermann and H. Gregor Molter
    December 2010, [DOI]
  • Daniel Ziener
    "Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs"
    University of Erlangen-Nuremberg, Germany, July 2010
  • Daniel Ziener, Florian Baueregger, and Jürgen Teich
    "Multiplexing Methods for Power Watermarking"
    In Proceedings of the IEEE Int. Symposium on Hardware-Oriented Security and Trust (HOST 2010), Anaheim, USA, 13 - 14 June 2010, [DOI]
  • Daniel Ziener, Florian Baueregger, and Jürgen Teich
    "Using the Power Side Channel of FPGAs for Communication"
    In Proceedings of the 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM1́0), 2 - 4 May 2010, [DOI]
  • Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, and Jürgen Teich
    "A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip"
    In Proceedings of Design and Test in Europe (DATE), 8 - 12 March 2010, [DOI]

2009

  • Daniel Ziener and Jürgen Teich
    "Concepts for Run-time and Error-resilient Control Flow Checking of Embedded RISC CPUs"
    Int. Journal of Autonomous and Adaptive Communications Systems, 256 — 275, July 2009, [DOI]
  • Volker Schöber, Oliver Bringmann, Andreas Herkersdorf, Walter Stechele, Norbert Wehn, Matthias May, Daniel Ziener, Abdelmajid Bouajila, Daniel Baldin, Johannes Zeppenfeld, Björn Sanders, Jürgen Teich, Maurice Sebastian, Rolf Ernst, and Dieter Treytnar
    "AIS - Autonomous Integrated Systems"
    newsletter edacentrum 04 2009, 5 — 13, April 2009

2008

  • Moritz Schmid, Daniel Ziener, and Jürgen Teich
    "Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs"
    In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2008), 8 - 10 December 2008, [DOI]
  • Daniel Ziener and Jürgen Teich
    "Concepts for Autonomous Control Flow Checking for Embedded CPUs"
    In Proceedings of the 5th International Conference on Autonomic and Trusted Computing (ATC-08), 23 - 25 June 2008, [DOI]
  • Daniel Ziener and Jürgen Teich
    "Power Signature Watermarking of IP Cores for FPGAs"
    Journal of Signal Processing Systems, 123 — 136, April 2008, [DOI]

2007

  • Daniel Ziener and Jürgen Teich
    "Watermarking Apparatus, Software Enabling an Implementation of an Electronic Circuit Comprising a Watermark, Method for Detecting a Watermark and Apparatus for Detecting a Watermark Europäisches Patent EP1835425, Anmeldetag 17.03.2006, veröffentlicht 19.09.2007, Patentklassen (IPC) G06F 17/50; G06F 21/00" (EP1835425)
    September 2007
  • Daniel Ziener and Jürgen Teich
    "Watermarking Apparatus, Software Enabling an Implementation of an Electronic Circuit Comprising a Watermark, Method for Detecting a Watermark and Apparatus for Detecting a Watermark. US-Patent US2007/0220263, Anmeldetag 19.10.2006 aus EP 1835425, veröffentlicht 20.09.2007, Patentklassen (IPC) H04L 9/00" (20070220263)
    September 2007
  • Walter Stechele, Oliver Bringmann, Rolf Ernst, Andreas Herkersdorf, Katharina Hojenski, Peter Janacik, Franz Rammig, Jürgen Teich, Norbert Wehn, Johannes Zeppenfeld, and Daniel Ziener
    "Concepts for Autonomic Integrated Systems"
    In Proceedings of edaWorkshop07, 19 - 20 June 2007
  • Walter Stechele, Oliver Bringmann, Rolf Ernst, Andreas Herkersdorf, Katharina Hojenski, Peter Janacik, Franz Rammig, Jürgen Teich, Norbert Wehn, Johannes Zeppenfeld, and Daniel Ziener
    "Autonomic MPSoCs for Reliable Systems"
    In Proceedings of Zuverlässigkeit und Entwurf (ZuD 2007), 27 - 28 March 2007

2006

  • Daniel Ziener and Jürgen Teich
    "FPGA Core Watermarking Based on Power Signature Analysis"
    In Proceedings of IEEE International Conference on Field-Programmable Technology (FPT 2006), 13 - 15 December 2006, [DOI]
  • Daniel Ziener, Stefan Aßmus, and Jürgen Teich
    "Identifying FPGA IP-Cores based on Lookup Table Content Analysis"
    In Proceedings of the International Conference on Field Programmable Logic and Applications Applications (FPL), 28 - 30 August 2006, [DOI]
  • Hans Adel, Gunter Hofmann, Rainer Wansch, and Daniel Ziener
    "A Method for Measuring Time Delay Behavior of Antennas"
    In Proceedings of First AMTA Europe Symposium, 1 - 4 May 2006

2005

  • Daniel Ziener and Jürgen Teich, University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design
    "Evaluation of Watermarking methods for FPGA-based IP-cores"
    March 2005